65C816 Instruction Set

Mnemonics are listed alphabetically. Instructions marked with “_*” are particular to the 65C816, the rest are also present on the 65C02. The table layout and arrangement is for presentation only. For the most part, “65C816” also applies to the 65c802.

References: 65c02 and 65c816 datasheets, “Programming the 65816: including the 6502, 65c02, and 65802” by David Eyes and Ron Lichty.

ADC

AND

ASL

BCC

BCS

BEQ

BIT

BMI

BNE

BPL

BRA

BRK

BRL

BVC

BVS

CLC

CLD

CLI

CLV

CMP

COP*

CPX

CPY

DEC

DEX

DEY

EOR

INC

INX

INY

JML*

JMP

JSL*

JSR

LDA

LDX

LDY

LSR

MVN*

MVP*

NOP

ORA

PEA*

PEI*

PER*

PHA

PHB*

PHD*

PHK*

PHP

PHX

PHY

PLA

PLB

PLD*

PLP

PLX

PLY

REP*

ROL

ROR

RTI

RTL*

RTS

SBC

SEC

SED

SEI

SEP*

STA

STP

STX

STY

STZ

SWA*

TAD*

TAS*

TAX

TAY

TCD*

TCS*

TDA*

TDC*

TRB

TSA*

TSB

TSC*

TSX

TXA

TXS

TXY

TYA

TYX*

WAI

WDM*

XBA*

XCE*

Adds the data located at the effective address specified by the operand to the contents of the accumulator. If the carry flag is set, another 1 is added to the accumulator. The final result is stored in the accumulator.

Flag	Effect on Execution	Value after Execution
c	1 = 1 is added to the result of the addition of the referenced value to the accumulator.	0 = valid unsigned result. 1 = unsigned overflow
d	0 = Binary addition is performed. 1 = BCD addition is performed.
i
m	0 = 16 bit accumulator, data from memory is 16 bits, with the low byte at the operand address and the high byte at the next address. 65c816 only. 1 = 8 bit accumulator, data from memory is 8 bits.
n		set to most significant bit of result
v		0 = valid signed result 1 = signed overflow
x
z		0 = result is nonzero 1 = result is zero

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	ADC addr	65c02	$6D	4 +1 if m=0 +1 if 65c02 and d=1	3
absolute indexed, x	ADC addr, X	65c02	$7D	4 +1 if page crossed +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary	3
absolute indexed, y	ADC addr, Y	65c02	$79	4 +1 if page crossed +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary	3
absolute long	ADC long	65c816	$6F	5 +1 if m=0	4
absolute long indexed, x	ADC long, X	65c816	$7F	5 +1 if m=0	4
direct page (dp)	ADC dp	65c02	$65	3 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
stack relative	ADC sr, S	65c816	$63	4 +1 if m=0	2
dp indexed, x	ADC dp, X	65c02	$75	4 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
dp indirect	ADC (dp)	65c02	$72	5 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
dp indirect long	ADC [dp]	65c816	$67	6 +1 if m=0 +1 if low byte of dp register is nonzero	2
sr indirect indexed, y	ADC (sr, S), Y	65c816	$73	7 +1 if m=0	2
dp indexed indirect, x	ADC (dp, X)	65c02	$61	6 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
dp indirect indexed, y	ADC (dp, Y)	65c02	$71	5 +1 if page crossed +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary +1 if low byte of dp register is nonzero	2
dp indirect long indexed, y	ADC [dp], Y	65c816	$77	6 +1 if m=0 +1 if low byte of dp register is nonzero	2
immediate	ADC #const	65c02	$69	2 +1 if m=0 +1 if 65c02 and d=1	2 +1 if m=0

Flag	Effect on Execution	Value after Execution
c
d
i
m	0 = 16 bit accumulator, data from memory is 16 bits, with the low byte at the operand address and the high byte at the next address. 65c816 only. 1 = 8 bit accumulator, data from memory is 8 bits.
n		set to most significant bit of result
v
x
z		0 = result is nonzero 1 = result is zero

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	AND addr	65c02	$2D	4 +1 if m=0	3
absolute indexed, x	AND addr, X	65c02	$3D	4 +1 if m=0 +1 if adding index crosses page boundary	3
absolute indexed, y	AND addr, Y	65c02	$39	4 +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary	3
absolute long	AND long	65c816	$2F	5 +1 if m=0	4
absolute long indexed, x	AND long, X	65c816	$3F	5 +1 if m=0	4
direct page (dp)	AND dp	65c02	$25	3 +1 if m=0 +1 if low byte of dp register is nonzero	2
stack relative	AND sr, S	65c816	$23	4 +1 if m=0	2
dp indexed, x	AND dp, X	65c02	$35	4 +1 if m=0 +1 if low byte of dp register is nonzero	2
dp indirect	AND (dp)	65c02	$32	5 +1 if m=0 +1 if low byte of dp register is nonzero	2
dp indirect long	AND [dp]	65c816	$27	6 +1 if m=0 +1 if low byte of dp register is nonzero	2
sr indirect indexed, y	AND (sr, S), Y	65c816	$23	7 +1 if m=0	2
dp indexed indirect, x	AND (dp, X)	65c02	$21	6 +1 if m=0 +1 if low byte of dp register is nonzero	2
dp indirect indexed, y	AND (dp, Y)	65c02	$31	5 +1 if m=0 +1 if adding index crosses page boundary +1 if low byte of dp register is nonzero	2
dp indirect long indexed, y	AND [dp], Y	65c816	$37	6 +1 if m=0 +1 if low byte of dp register is nonzero	2
immediate	AND #const	65c02	$29	2 +1 if m=0	2 +1 if m=0

Shift the contents of the location specified by the operand left one bit. The most significant bit is transferred into the carry flag, while the least significant bit is cleared. This effectively multiplies the value by two.

Flag	Effect on Execution	Value after Execution
c		High bit is shifted into carry.
d
i
m	0 = 16 bit accumulator, data from memory is 16 bits, with the low byte at the operand address and the high byte at the next address. 65c816 only. 1 = 8 bit accumulator, data from memory is 8 bits.
n		set to most significant bit of result
v
x
z		0 = result is nonzero 1 = result is zero

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
accumulator	ASL A	65c02	$0A	2	1
absolute	ASL addr	65c02	$0E	6 +1 if m=0	3
absolute indexed, x	ASL addr, X	65c02	$1E	7 +1 if m=0 -1 if 65c02 and no page boundary crossed	3
direct page (dp)	ASL dp	65c02	$06	5 +1 if m=0 +1 if low byte of dp register is nonzero	2
dp indexed, x	ASL dp, X	65c02	$35	2 +1 if m=0 +1 if low byte of dp register is nonzero	6

The carry flag is tested and, if it is clear, a branch is taken. If it is set, execution continues with the instruction immediately following the two-byte BCC instruction.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

After a comparison or subtraction, if the accumulator is less than the operand, BCC will branch.

Flag	Effect on Execution	Value after Execution
c	Instruction will branch if c = 0, it will fall through to the next instruction if c = 1.
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative	BCC offset	65c02	$90	2 +1 if branch taken +1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1	2

The carry flag is tested and, if set, a branch is taken. If it is clear, the instruction immediately following the two-byte BCS instruction is executed.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

After a comparison or subtraction, if the accumulator is greater than or equal to the operand, BCS will branch.

Flag	Effect on Execution	Value after Execution
c	Instruction will branch if c = 1, it will fall through to the next instruction if c = 0.
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative	BCS offset	65c02	$B0	2 +1 if branch taken +1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1	2

The zero flag is tested. If it is set, a branch is taken. If it is clear, the instruction immediately following the two-byte BEQ is executed.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

After a comparison or subtraction, if the accumulator is equal to the operand, or if an instruction results in 0, such as a decrement from one, BEQ will branch.

Flag	Effect on Execution	Value after Execution
c
d
i
m
n
v
x
z	Instruction will branch if z = 1, it will fall through to the next instruction if z = 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative	BEQ offset	65c02	$F0	2 +1 if branch taken +1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1	2

Sets the status register flags based on the result of two different operations:

1. Sets or clears the n flag to reflect the value of the high bit of the data located at the effective address specified by the operand, and sets or clears the v flag to reflect the contents of the next-to-highest bit of the data addressed.
2. Logically ANDs the data located at the effective address with the contents of the accumulator; it changes neither value, but sets the z flag if the result is zero, or clears it if the result is non-zero.

BIT is usually used immediately preceding a conditional branch instruction: to test a memory value’s highest or next-to-highest bits; with a mask in the accumulator, to test any bits of the memory operand; or with a constant as the mask (using immediate addressing) or a mask in memory, to test any bits in the accumulator. All of these tests are non-destructive of the data in the accumulator or in memory. When the BIT instruction is used with the immediate addressing mode, the n and v flags are unaffected.

Flag	Effect on Execution	Value after Execution
c
d
i
m	0 = 16 bit accumulator, data from memory is 16 bits, with the low byte at the operand address and the high byte at the next address. 65c816 only. Bit 15 is moved into the n flag and bit 14 is moved into the v flag. 1 = 8 bit accumulator, data from memory is 8 bits.
n		Value of most significant bit of memory data.
v		Value of next-most-significant bit of memory data.
x
z		1 = logical AND of memory and accumulator is zero, 0 = logical AND of memory and accumulator <> 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	BIT add	65c02	$2C	2 +1 if m = 0	2 +1 if m = 0
absolute indexed, x	BIT add, X	65c02	$3c	4 +1 if m = 0 +1 if adding index crosses page boundary	3
direct page (dp)	BIT dp	65c02	$24	4 +1 if m = 0 +1 if low byte of dp register <> 0	3
dp indexed, x	BIT dp, X	65c02	$34	4 +1 if m = 0 +1 if low byte of dp register <> 0	2
immediate	BIT #const	65c02	$89	2 +1 if m = 0	2 +1 if m = 0

The negative flag is tested. If it is set, the branch is taken. A number with its high bit set may be interpreted as a negative twos-complement number, so this instruction tests, among other things, for the sign of two’s-complement numbers. If the negative flag is clear, the instruction immediately following the two-byte BMI instruction is executed.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

Flag	Effect on Execution	Value after Execution
c
d
i
m
n	branches if n = 1, continues with the next instruction after the BMI if n = 0
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative	BMI offset	65c02	$30	2 +1 if branch taken +1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1	2

The zero flag is tested. If it is clear, a branch is taken. If it is set, the instruction immediately following the two-byte BNE is executed.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

After a comparison or subtraction, if the accumulator is not equal to the operand, or if an instruction results in a non-zero, such as an increment from zero, BNE will branch.

Flag	Effect on Execution	Value after Execution
c
d
i
m
n
v
x
z	Instruction will branch if z = 0, it will fall through to the next instruction if z = 1.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative	BNE offset	65c02	$D0	2 +1 if branch taken +1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1	2

The negative flag is tested. If it is clear, a branch is taken. In the two’s-complement system, values with their high byte clear are interpreted as positive numbers. If the flag is set, the branch is not taken and the instruction following the two-byte BPL is executed. In two’s-complement, this means the number was negative.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

Flag	Effect on Execution	Value after Execution
c
d
i
m
n	0 = branch is taken 1 = branch is not taken, next instruction is executed.
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative	BPL offset	65c02	$10	2 +1 if branch taken +1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1	2

This is similar to an unconditional JMP, but with signed displacements instead of absolute addresses. This makes this instruction relocatable.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

Flag	Effect on Execution	Value after Execution
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative	BRA offset	65c02	$80	3 +1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1	2

Force a software interrupt. BRK is unaffected by the interrupt disable flag. Although BRK is a one-byte instruction, the program counter (which is pushed onto the stack by the instruction) is incremented by two. This lets you follow the break instruction with a signature byte indicating which break caused the interrupt. This byte must always be present, even if not used, OR the return address on the stack decremented to account for its absence and allow the RTI to work properly.

On the 65c02 and in 65c816 emulation mode, the program counter is incremented by two, then pushed onto the stack; the status register, with the b break flag set, is pushed onto the stack; the interrupt disable flag is set; and the program counter is loaded from the interrupt vector at $FFFE-FFFF.

It is up to the interrupt handling routine at this address to check the b flag in the stacked status register to determine if the interrupt was caused by a software interrupt (BRK) or by a hardware IRQ, which shares the BRK vector but pushes the status register onto the stack with the b break flag clear. For example:

PLA       ; copy status from top of stack
PHA
AND #$10  ; check brk bit
BNE IsBRK ; branch if set

On the 65c816, the program counter bank register is pushed onto the stack; the program counter is incremented by two and pushed onto the stack; the status register is pushed onto the stack; the interrupt disable flag is set; the program bank register is cleared to zero; and the program counter is loaded from the break vector at $OOFFE6-OOFFE7.

Flag	Effect on Execution	Value after Execution
b		on the 65c02 and 65c816 in emulation mode, set when pushed onto the stack before calling the interrupt service routine.
c
d		reset to 0 after BRK is executed.
i		set to 1, disabling hardware IRQs
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack/interrupt	BRK	65c02	$00	7 +1 if 65816 if e = 0	2 instruction is 1 byte, but program counter value pushed onto the stack is incremented by 2 allowing for signature byte

Similarly to BRA, this instruction always branches. Unlike BRA, the displacement is a signed 16 bit value, not a signed 8 bit value. The allowable range of the displacement is anywhere within the current 64K program bank. This is a relocatable branch instruction.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative long	BRL label	65c816	$82	4	3

This instruction branches if the overflow flag is clear. If the overflow flag is set, the next instruction after the two-byte BVC is executed. The overflow flag is altered by only four instructions on the 65c02: addition, subtraction, CLV and BIT and two further instructions, SEP and REP on the 65816. The flag can also be set by a hardware pin on the processor.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v	0 = instruction will branch 1 = instruction will not branch
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative	BVC offset	65c02	$50	2 +1 if branch taken +1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1	2

This instruction branches if the overflow flag is set. If it is clear, the next instruction following the two-byte BVS is executed. The overflow flag is altered by only four instructions on the 65c02: addition, subtraction, CLV and BIT and two further instructions, SEP and REP on the 65816. The flag can also be set by a hardware pin on the processor. BVS is used almost exclusively to determine if a two’s-complement arithmetic calculation has overflowed, much as the carry is used to determine if an unsigned arithmetic calculation has overflowed. (Note, however, that the compare instructions do not affect the overflow flag.) You can also use BVS to test the second-highest bit in a value by using it after the BIT instruction, which moves the second-highest bit of the tested value into the v flag.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v	0 = instruction will not branch 1 = instruction will branch
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
program counter relative	BVS offset	65c02	$70	2 +1 if branch taken +1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1	2

This instruction can be used prior to an addition to prevent the carry flag from affecting the result. Used prior to BCC, it will force a branch and on the 65816, it is used along with XCE to put the 65816 into emulation mode.

Flag	Effect on Execution	Value after Execution
b
c		0
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	CLC	65c02	$18	2	1

This instruction clears the d flag, which turns off Binary Coded Decimal mode. Use this when ADC and SBC need to operate on binary data rather than BCD data.

Flag	Effect on Execution	Value after Execution
b
c
d		0
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	CLD	65c02	$D8	2	1

Clears the interrupt disable bit in the flags register. This enables interrupt handling. The processor sets the interrupt disable flag when an interrupt service routine is called and restores it when the subsequent RTI instruction is executed.

Flag	Effect on Execution	Value after Execution
b
c
d
i		0
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	CLI	65c02	$58	2	1

Clears the overflow flag. There is no instruction to explicitly set the overflow flag. This can be accomplished through hardware via the Set Overflow pin, as can a BIT instruction with bit 6 set.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v		0
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	CLV	65c02	$B8	2	1

Compares the data referenced by the parameter to the contents of the accumulator. This is an internal subtraction operation where the data is subtracted from the accumulator and the processor flags are set accordingly. The result of the subtraction is discarded, neither the referenced data nor the accumulator are changed. Note also that the value of the carry flag is not used in the operation and the overflow flag is not set, this means CMP only good for unsigned comparisons.

Flag	Effect on Execution	Value after Execution
b
c		1 = no borrow required (accumulator >= data). 0 = borrow required (accumulator < data).
d
i
m	0 = comparison is 16 bits on 65816. 1 = comparison is 8 bits on 65816.
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	ADC addr	65c02	$6D	4 +1 if m=0 +1 if 65c02 and d=1	3
absolute indexed, x	ADC addr, X	65c02	$7D	4 +1 if page crossed +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary	3
absolute indexed, y	ADC addr, Y	65c02	$79	4 +1 if page crossed +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary	3
absolute long	ADC long	65c816	$6F	5 +1 if m=0	4
absolute long indexed, x	ADC long, X	65c816	$7F	5 +1 if m=0	4
direct page (dp)	ADC dp	65c02	$65	3 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
stack relative	ADC sr, S	65c816	$63	4 +1 if m=0	2
dp indexed, x	ADC dp, X	65c02	$75	4 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
dp indirect	ADC (dp)	65c02	$72	5 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
dp indirect long	ADC [dp]	65c816	$67	6 +1 if m=0 +1 if low byte of dp register is nonzero	2
sr indirect indexed, y	ADC (sr, S), Y	65c816	$73	7 +1 if m=0	2
dp indexed indirect, x	ADC (dp, X)	65c02	$61	6 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
dp indirect indexed, y	ADC (dp, Y)	65c02	$71	5 +1 if page crossed +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary +1 if low byte of dp register is nonzero	2
dp indirect long indexed, y	ADC [dp], Y	65c816	$77	6 +1 if m=0 +1 if low byte of dp register is nonzero	2
immediate	ADC #const	65c02	$69	2 +1 if m=0 +1 if 65c02 and d=1	2 +1 if m=0

This instruction generates a software interrupt that jumps to a COP vector ($FFF4, $FFF5) and is unaffected by the interrupt disable flag, i. COP may also be trapped by a co-processor. As with BRK, the COP instruction increments the program counter by two, providing a byte after the opcode to use as an identifier. Identifiers in the range $80 to $FF are reserved by Western Design Center. Identifiers in the range $00 to $79 are available for use by software interrupt handlers.

Flag	Effect on Execution	Value after Execution
b
c
d		0 – decimal mode is disabled.
e	0 = pc incremented by 2 and pushed onto stack, status register pushed on stack, irq disable flag set, pc is loaded from $fff4, $fff5. 1 = program counter bank register is pushed onto the stack, pc is incremented by 2 and pushed on stack, status register pushed on stack, irq disable flag set, program bank register is cleared to 0, pc is loaded from $00ffe4, $00ffe5.
i		1 – interrupts are disabled when the ISR is called.
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack/interrupt	COP const	65c816	$B8	7 +1 if e=0.	1 +1 for optional identifier byte.

Compares the data referenced by the parameter to the contents of the X register. This is an internal subtraction operation where the data is subtracted from the X register and the processor flags are set accordingly. The result of the subtraction is discarded, neither the referenced data nor the X register are changed. Note also that the value of the carry flag is not used in the operation and the overflow flag is not set, this means CPX only good for unsigned comparisons.

Flag	Effect on Execution	Value after Execution
b
c		1 = no borrow required (x register >= data). 0 = borrow required (x register < data).
d
i
m
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x	0 = comparison is 16 bits on 65816. 1 = comparison is 8 bits on 65816.
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	CPX addr	65c02	$EC	4 +1 if x=0.	3
direct page (dp)	CPX dp	65c02	$E4	3 +1 if x = 0. +1 if low byte of dp register <> 0.	2
immediate	CPX #const	65c02	$E0	2 +1 if x = 0.	2 +1 if x = 0.

Compares the data referenced by the parameter to the contents of the Y register. This is an internal subtraction operation where the data is subtracted from the Y register and the processor flags are set accordingly. The result of the subtraction is discarded, neither the referenced data nor the Y register are changed. Note also that the value of the carry flag is not used in the operation and the overflow flag is not set, this means CPY only good for unsigned comparisons.

Flag	Effect on Execution	Value after Execution
b
c		1 = no borrow required (y register >= data). 0 = borrow required (y register < data).
d
i
m
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x	0 = comparison is 16 bits on 65816. 1 = comparison is 8 bits on 65816.
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	CPY addr	65c02	$CC	4 +1 if x=0.	3
direct page (dp)	CPY dp	65c02	$C4	3 +1 if x = 0. +1 if low byte of dp register <> 0.	2
immediate	CPY #const	65c02	$C0	2 +1 if x = 0.	2 +1 if x = 0.

Decrements the contents of the location specified by the operand, or the accumulator. DEC is not affected by the carry flag, nor does it set it. DEC does set the zero and negative flags. DEC is not affected by the d flag.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m	0 = Data decremented is 16 bits. 1 and 65c02 = Data decremented is 8 bits.
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
accumulator	DEC A	65c02	$3A	2	1
absolute	DEC addr	65c02	$CE	6 +2 if m = 0.	1
absolute indexed, x	DEC addr, X	65c02	$DE	7 +1 if m = 0. -1 if 65c02 and no page boundary crossed.	3
direct page (dp)	DEC dp	65c02	$C6	5 +2 if m = 0. +1 if low byte of dp register <> 0.	2
dp indexed, x	DEC dp, X	65c02	$D6	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2

Decrement the contents of the index register X by one. DEX does not affect the carry flag, nor is it affected by it. DEX does set the n and z flags.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x	0 = Data decremented is 16 bits. 1 and 65c02 = Data decremented is 8 bits.
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	DEX	65c02	$CA	2	1

Decrement the contents of the index register Y by one. DEY does not affect the carry flag, nor is it affected by it. DEY does set the n and z flags.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x	0 = Data decremented is 16 bits. 1 and 65c02 = Data decremented is 8 bits.
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	DEY	65c02	$88	2	1

Bitwise logical “Exclusive OR” the data specified with the contents of the accumulator, placing the result in the accumulator.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m	0 = Data is 16 bits. 1 and 65c02 = Data is 8 bits.
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	EOR addr	65c02	$4D	4 +1 if m = 0.	3
absolute indexed, x	EOR addr, X	65c02	$5D	4 +1 if m = 0. +1 if adding index crosses page boundary.	3
absolute indexed, y	EOR addr, Y	65c02	$59	4 +1 if m = 0. +1 if adding index crosses page boundary.	3
absolute long	EOR long	65c816	$4F	5 +1 if m = 0.	4
absolute long indexed, x	EOR long, X	65c816	$5F	5 +1 if m = 0.	4
direct page (dp)	EOR dp	65c02	$45	3 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indexed, x	EOR dp, X	65c02	$55	4 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indexed indirect, x	EOR (dp, X)	65c02	$41	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indirect	EOR (dp)	65c02	$52	5 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indirect indexed, y	EOR [dp], Y	65c816	$57	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indirect long	EOR [dp]	65c816	$47	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2
immediate	EOR #const	65c02	$49	2 +1 if m = 0.	2 +1 if m = 0.
stack relative (sr)	EOR sr, S	65c816	$43	7 +1 if m = 0.	2
sr indirect indexed, y	EOR (sr, S), Y	65c816	$53	7 +1 if m = 0.	2

Increments the contents of the location specified by the operand, or the accumulator. INC is not affected by the carry flag, nor does it set it. INC does set the zero and negative flags. INC is not affected by the d flag.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m	0 = Data incremented is 16 bits. 1 and 65c02 = Data incremented is 8 bits.
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
accumulator	INC A	65c02	$1A	2	1
absolute	INC addr	65c02	$EE	6 +2 if m = 0.	1
absolute indexed, x	INC addr, X	65c02	$FE	7 +1 if m = 0. -1 if 65c02 and no page boundary crossed.	3
direct page (dp)	INC dp	65c02	$E6	5 +2 if m = 0. +1 if low byte of dp register <> 0.	2
dp indexed, x	INC dp, X	65c02	$F6	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2

Increment the contents of the index register X by one. INX does not affect the carry flag, nor is it affected by it. INX does set the n and z flags.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x	0 = Data incremented is 16 bits. 1 and 65c02 = Data incremented is 8 bits.
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	INX	65c02	$E8	2	1

Increment the contents of the index register Y by one. INY does not affect the carry flag, nor is it affected by it. INY does set the n and z flags.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		1 = most significant bit of result is set. 0 = most significant bit of result is not set.
v
x	0 = Data incremented is 16 bits. 1 and 65c02 = Data incremented is 8 bits.
z		1 = result is zero. 0 = result is non-zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	INY	65c02	$C8	2	1

The program counter and program counter bank are loaded with the address given in the operand and execution resumes from there.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute indirect long	JML [addr]	65c816	$DC	6	3
absolute long	JML long	65c816	$5C	4	4

The program counter is loaded with the address given in the operand and execution resumes from there.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	JMP addr	65c02	$4C	3	3
absolute indexed indirect	JMP (addr, X)	65c02	$7C	6	3
absolute indirect	JMP (addr)	65c02	$6C	5 +1 if 65c02	3
absolute indirect long	JMP [addr] or JML [addr]	65c816	$DC	6	3
absolute long	JMP long or JML long	65c816	$5C	4	4

Transfers control to the subroutine specified by the 24-bit operand. The current 24-bit return address is pushed onto the stack before the jump is executed. The return address is the address of the last byte of this instruction (so, the actual return address -1). The current program counter bank is pushed first, then the high byte and then low byte of the return address.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute long	JSL long or JSR long	65c816	$5C	8	4

Transfers control to the subroutine specified by the operand. The current return address is pushed onto the stack before the jump is executed. The return address is the address of the last byte of this instruction (so, the actual return address -1). The current program counter bank is pushed first if a long address is used (address > $FFFF), then the high byte and then low byte of the return address.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	JSR addr	65c02	$20	6	3
absolute indexed indirect	JSR (addr, X)	65c02	$FC	8	3
absolute long	JSR long or JSL long	65c816	$22	8	4

Loads the data located at the specified address into the accumulator.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m	m = 0 on 65c816, then data is 16-bit.
n		most significant bit of data.
v
x
z		1 = data = 0. 0 = data <> 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	LDA addr	65c02	$AD	4 +1 if m = 0.	3
absolute indexed, x	LDA addr, X	65c02	$BF	4 +1 if m = 0. +1 if adding index crosses page boundary.	3
absolute indexed, y	LDA addr, Y	65c02	$B9	4 +1 if m = 0. +1 if adding index crosses page boundary.	3
absolute long	LDA long	65c816	$AF	5 +1 if m = 0.	4
absolute long indexed, x	LDA long, X	65c816	$BF	5 +1 if m = 0.	4
direct page (dp)	LDA dp	65c02	$A5	3 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indexed, x	LDA dp, X	65c02	$B5	4 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indexed indirect, x	LDA (dp, X)	65c02	$A1	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indirect	LDA (dp)	65c02	$B2	5 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indirect indexed, y	LDA (dp), Y	65c816	$B1	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indirect long	LDA [dp]	65c816	$A7	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indirect long indexed, y	LDA [dp], Y	65c816	$B7	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2
immediate	LDA #const	65c02	$A9	2 +1 if m = 0.	2 +1 if m = 0.
stack relative (sr)	LDA sr, S	65c816	$A3	7 +1 if m = 0.	2
sr indirect indexed, y	LDA (sr, S), Y	65c816	$B3	7 +1 if m = 0.	2

Loads the data located at the specified address into the X index register.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		most significant bit of data.
v
x	x = 0 on 65c816, then data is 16-bit.
z		1 = data = 0. 0 = data <> 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	LDX addr	65c02	$AE	4 +1 if x = 0.	3
absolute indexed, y	LDX addr, Y	65c02	$BE	4 +1 if x = 0. +1 if adding index crosses page boundary.	3
direct page (dp)	LDX dp	65c02	$A6	3 +1 if x = 0. +1 if low byte of dp register <> 0.	2
dp indexed, y	LDX dp, Y	65c816	$B6	4 +1 if x = 0. +1 if low byte of dp register <> 0.	2
immediate	LDX #const	65c02	$A2	2 +1 if x = 0.	2 +1 if x = 0.

Loads the data located at the specified address into the Y index register.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		most significant bit of data.
v
x	x = 0 on 65c816, then data is 16-bit.
z		1 = data = 0. 0 = data <> 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	LDY addr	65c02	$AC	4 +1 if x = 0.	3
absolute indexed, x	LDY addr, X	65c02	$BC	4 +1 if x = 0. +1 if adding index crosses page boundary.	3
direct page (dp)	LDY dp	65c02	$A4	3 +1 if x = 0. +1 if low byte of dp register <> 0.	2
dp indexed, x	LDY dp, X	65c02	$B4	4 +1 if x = 0. +1 if low byte of dp register <> 0.	2
immediate	LDY #const	65c02	$A0	2 +1 if x = 0.	2 +1 if x = 0.

This is the arithmetic equivalent of unsigned division by 2. The bits in the location specified by the operand are shifted one bit to the right. The lowest-significant bit is shifted into the carry flag. 0 is shifted into the most-significant bit.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m	m = 0 on 65c816, then data is 16-bit.
n
v
x
z		1 = data = 0. 0 = data <> 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	LSR addr	65c02	$4E	6 +1 if m = 0.	3
absolute indexed, x	LSR addr, X	65c02	$5E	7 +1 if m = 0. -1 if 65c02 and no page boundary crossed.	3
accumulator	LSR A	65c02	$4A	2	1
direct page (dp)	LSR dp	65c02	$46	5 +1 if m = 0. +1 if low byte of dp register <> 0.	2
dp indexed, x	LSR dp, X	65c02	$56	6 +1 if m = 0. +1 if low byte of dp register <> 0.	2

Copies a block of memory from a source address to a target address. This differs from MVP in that the source and target addresses are interpreted by MVN as the start of the memory block. Bytes are copied from incrementing source addresses to incrementing target addresses until the specified number of bytes + 1 have been copied. The source address is put in index X, the target address is put in index Y and the number of bytes to copy – 1 is put in the accumulator. The operands to the instruction are the source bank and destination bank.

If the source and target areas overlap, this instruction should only be used if the target address is lower than the source address. If the target is higher than the source address, then use MVP.

In 6502 emulation mode, the bank operands should always be 0.

If a block move is interrupted, it may be resumed automatically upon an RTI instruction if all registers are restored or intact. The current byte copy is completed before an interrupt is serviced.

For example:

would be equivalent to:

; incrementing addresses
lda $0000
sta $0200
lda $0001
sta $0201
lda $0002
sta $0202


Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
block move	MVN srcbk, destbk	65c816	$54	7 cycles per byte copied.	3

Copies a block of memory from a source address to a target address. This differs from MVN in that the source and target addresses are interpreted by MVP as the end of the memory block. Bytes are copied from decrementing source addresses to decrementing target addresses until the specified number of bytes + 1 have been copied. The source address is put in index X, the target address is put in index Y and the number of bytes to copy – 1 is put in the accumulator. The operands to the instruction are the source bank and destination bank.

If the source and target areas overlap, this instruction should only be used if the target address is higher than the source address. If the target is lower than the source address, then use MVN.

In 6502 emulation mode, the bank operands should always be 0.

If a block move is interrupted, it may be resumed automatically upon an RTI instruction if all registers are restored or intact. The current byte copy is completed before an interrupt is serviced.

For example:

; source = $0000
; target = $0200
; bytes to copy = 3
ldx #$0200
ldy #$0000
lda #$0002 ; bytes to copy - 1
mvn #$00, #$00

would be equivalent to:

; decrementing addresses
lda $0202
sta $0002
lda $0201
sta $0001
lda $0200
sta $0000

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
block move	MVP srcbk, destbk	65c816	$44	7 cycles per byte copied.	3

Takes no action other than to advance the program counter. No flags or memory are affected.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	NOP	65c02	$EA	2	1

Performs a bitwise logical “OR” of the data located at the effective address specified by the operand with the contents of the accumulator, placing the result in the accumulator.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m	0 = 16 bit data/accumulator. 1 and 65c02 = 8 bit data/accumulator.
n		1 = most significant bit of result.
v
x
z		0 = result is non-zero. 1 = result is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	ORA addr	65c02	$0D	4 +1 if m=0 +1 if 65c02 and d=1	3
absolute indexed, x	ORA addr, X	65c02	$1D	4 +1 if page crossed +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary	3
absolute indexed, y	ORA addr, Y	65c02	$19	4 +1 if page crossed +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary	3
absolute long	ORA long	65c816	$0F	5 +1 if m=0	4
absolute long indexed, x	ORA long, X	65c816	$1F	5 +1 if m=0	4
direct page (dp)	ORA dp	65c02	$05	3 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
stack relative	ORA sr, S	65c816	$03	4 +1 if m=0	2
dp indexed, x	ORA dp, X	65c02	$15	4 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
dp indirect	ORA (dp)	65c02	$12	5 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
dp indirect long	ORA [dp]	65c816	$07	6 +1 if m=0 +1 if low byte of dp register is nonzero	2
sr indirect indexed, y	ORA (sr, S), Y	65c816	$13	7 +1 if m=0	2
dp indexed indirect, x	ORA (dp, X)	65c02	$01	6 +1 if m=0 +1 if 65c02 and d=1 +1 if low byte of dp register is nonzero	2
dp indirect indexed, y	ORA (dp, Y)	65c02	$11	5 +1 if page crossed +1 if m=0 +1 if 65c02 and d=1 +1 if adding index crosses page boundary +1 if low byte of dp register is nonzero	2
dp indirect long indexed, y	ORA [dp], Y	65c816	$17	6 +1 if m=0 +1 if low byte of dp register is nonzero	2
immediate	ORA #const	65c02	$09	2 +1 if m=0 +1 if 65c02 and d=1	2 +1 if m=0

Pushes the 16-bit operand onto the stack. The stack pointer is decremented twice and this instruction always pushes 16 bits of data, regardless of the m and x flag settings. Note that this instruction pushes the actual operand onto the stack, not the data stored at the address denoted by the operand.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (absolute)	PEA addr	65c816	$F4	3	5

Pushes the 16-bit value located at the address formed by adding the direct page offset specified by the operand to the direct page register. The data doesn’t necessarily have to be an address. This instruction always pushes 16 bits of data, regardless of the setting of the m and x flags. The effective indirect address, rather than the data stored at the address is what is pushed onto the stack.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (direct page indirect)	PEI (dp)	65c816	$D4	6 +1 if low byte of dp register <> 0	2

Adds the current value of the program counter to the 16-bit unsigned displacement in the operand and pushes the result onto the stack. This instruction always pushes 16 bits, regardless of the settings of the m and x flags.

This instruction is helpful in writing relocatable code, in which an address within the program must be accessed. The address pushed onto the stack will be the runtime address of the data area, regardless of where the program was loaded in memory. It may be pulled into a register, stored in an indirect pointer or used on the stack with the stack relative indirect indexed addressing mode to access the data at that location.

The syntax used is to specify as the operand the label of the data area you want to reference. This location must be in the program bank, since the displacement is relative to the program counter. The assembler converts the assembly-time label into a displacement from the assembly-time address of the next instruction.

The value of the program counter used in the addition is the address of the next instruction (the instruction following the PER instruction).

PER can also be used to push return addresses onto the stack, either as part of a simulated branch-to-subroutine or to place the return address beneath the stacked parameters to a subroutine call. Not that a pushed return address should be the desired return address minus one.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (program counter relative long)	PER label	6c816	$62	3	6

Pushes the accumulator onto the stack.

$01ff (s register, top of stack) ->

xx

$01ff	8 bit accumulator contents
$01fe (s register, after pha) ->	xx

$01ff	upper 8 bits of accumulator contents
$01fe	lower 8 bits of accumulator contents
$01fd (s register, after pha) ->	xx

Flag	Effect on Execution	Value after Execution
b
c
d
i
m	0 = data pushed is 16 bits. 1 or on 65c02 = data pushed is 8 bits.
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (push)	PHA	65c02	$48	3 +1 if m = 0	1

Pushes the contents of the data bank register onto the stack. This is only one byte, no matter the value of the m and x flags.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (push)	PBH	65c816	$8B	3	1

Pushes the contents of the direct page register onto the stack. This is always a 16-bit operation, regardless of the setting of the m and x flag.

By pushing the D register onto the stack, the local environment of a calling subroutine may easily be saved by a called subroutine before modifying the D register to provide islets with its own direct page memory.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (push)	PHB	65c816	$0B	4	1

Pushes the program bank register onto the stack. This is always an 8-bit value, regardless of the setting of m and x.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (push)	PHK	65c816	$4B	3	1

Push the contents of the processor status register onto the stack. This is always an 8-bit value, regardless of the setting of the m and x flags. This does not preserve the e flag. The only way to access the e flag is via the XCE instruction.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (push)	PHP	65c02	$08	3	1

$01ff (s register, top of stack) ->

xx

$01ff	8 bit register x contents
$01fe (s register, after phi) ->	xx

$01ff	upper 8 bits of register x contents
$01fe	lower 8 bits of register x contents
$01fd (s register, after phx) ->	xx

Flag	Effect on Execution	Value after Execution
b
c
d
i
m	0 = data pushed is 16 bits. 1 or on 65c02 = data pushed is 8 bits.
n
v
x
z

Pushes the contents of the X index register onto the stack. This will either push 8 bits or 16 bits of data, depending on the x flag.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x	0 = 16 bits of data pushed. 1 and on 65c02 = 8 bits pushed.
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (push)	PHX	65c02	$DA	3 +1 if x = 0.	1

Pushes the contents of the Y index register onto the stack. This will either push 8 bits or 16 bits of data, depending on the x flag.

$01ff (s register, top of stack) ->

xx

$01ff	8 bit register y contents
$01fe (s register, after phy) ->	xx

$01ff	upper 8 bits of register y contents
$01fe	lower 8 bits of register y contents
$01fd (s register, after phy) ->	xx

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x	0 = 16 bits of data pushed. 1 and on 65c02 = 8 bits pushed.
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (push)	PHY	65c02	$5a	3 +1 if x = 0	1

Pulls the value in the top of the stack into the accumulator.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m	0 = 16 bits are pulled. 1 and on 65c02 = 8 bits are pulled.
n		set to the most significant bit of the pulled data.
v
x
z		0 = value pulled is nonzero 1 = value pulled is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (pull)	PLA	65c02	$68	4 +1 if m = 0	1

Pulls the 8-bit value on top of the stack into the data bank register B, switching the data bank to that value. This is the only instruction that can modify the data bank register. Since the data bank register is only 8 bits, this instruction always pulls 8 bits from the stack, regardless of the setting of the m and x flags.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		set to the most significant bit of the data bank register.
v
x
z		0 = value pulled is nonzero. 1 = value pulled is 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (pull)	PLB	65c816	$AB	4	1

Pull the 16 bit value on top of the stack into the direct page register D, switching the direct page to that value. PLD is typically used to restore the direct page register to a previous value.

Since the direct page register is a 16-bit register, two bytes are always pulled from the stack, regardless of the value of the m and x flags.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		most significant bit of the pulled value.
v
x
z		0 = pulled value is nonzero. 1 = pulled value is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (pull)	PLD	65c816	$2B	5	1

Pulls the 8-bit value on the top of the stack into the processors status register P, switching the status byte to that value.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (pull)	PLP	65c02	$28	4	1

Pulls the value on the top of the stack into the X index register.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		set to the most significant bit of the data.
v
x	0 = 16 bits are pulled. 1 and always on 65c02 = 8 bits are pulled.
z		0 = pulled data is nonzero. 1 = pulled data is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (pull)	PLX	65c02	$FA	4 +1 if x = 0.	1

Pulls the value on the top of the stack into the Y index register.

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n		set to the most significant bit of the data.
v
x	0 = 16 bits are pulled. 1 and always on 65c02 = 8 bits are pulled.	0 = pulled data is nonzero. 1 = pulled data is zero.
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (pull)	PLY	65c02	$7A	4 +1 if x = 0.	1

This instruction takes a bit mask as an operand. Each bit that is set in the operand will cause the corresponding bit in the status register to reset to 0. If a bit in the mask operand is 0, the corresponding bit in the status register remains unchanged.

7	6	5	4	3	2	1	0
n	v	m	x	d	i	z	c
negative	overflow	8 bit memory/accumulator	8 bit index registers	decimal	irq interrupt disable	zero result	carry

Flag	Effect on Execution	Value after Execution
c		0 = bit 0 is set in the REP operand. otherwise, unchanged
d		0 = bit 3 is set in the REP operand. otherwise, unchanged.
e	0 = all flags are modifiable. 1 = the break flag and bit 5 are unaffected by REP.
i		0 = bit 2 is set in the REP operand. otherwise, unchanged.
m		0 = bit 5 is set in the REP operand. otherwise, unchanged.
n		0 = bit 7 is set in the REP operand. otherwise, unchanged.
v		0 = bit 6 is set in the REP operand. otherwise, unchanged.
x		0 = bit 4 is set in the REP operand. otherwise, unchanged.
z		0 = bit 1 is set in the REP operand. otherwise, unchanged.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
immediate	REP #const	65c816	$C2	3	2

Rotate the contents of the location specified by the operand left one bit. Bit 0 will take the value in the carry flag and the carry flag will receive the value of the most significant bit.

Flag	Effect on Execution	Value after Execution
b
c		the original most significant bit
d
i
m	0 = 16 bits of data are rotated. 1 and 65c02 = 8 bits are rotated.
n		most significant bit of result.
v
x
z		0 = result is non-zero. 1 = result is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	ROL addr	65c02	$2E	6 +2 if m = 0.	3
absolute indexed, x	ROL addr, X	65c02	$3E	7 +2 if m = 0. -1 if 65c02 and no page boundary crossed.	3
accumulator	ROL	65c02	$2A	2	1
direct page (dp)	ROL dp	65c02	$26	5 +2 if m = 0. +1 if low byte of dp register <> 0.	2
dp indexed, x	ROL dp, X	65c02	$36	6 +2 if m = 0. +1 if low byte of dp register <> 0.	2

Rotate the contents of the location specified by the operand right one bit. The most significant bit will take the value in the carry flag and the carry flag will receive the value of the least significant bit (bit 0).

Flag	Effect on Execution	Value after Execution
b
c		least significant bit of original value
d
i
m	0 = 16 bits of data are rotated. 1 and 65c02 = 8 bits of data are rotated.
n		most significant bit of result.
v
x
z		0 = result is non-zero. 1 = result is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	ROR addr	65c02	$6E	6 +2 if m = 0.	3
absolute indexed, x	ROR addr, X	65c02	$7E	7 +2 if m = 0. -1 if 65c02 and no page boundary crossed.	3
accumulator	ROR	65c02	$6A	2	1
direct page (dp)	ROR dp	65c02	$66	5 +2 if m = 0. +1 if low byte of dp register <> 0.	2
dp indexed, x	ROR dp, X	65c02	$76	6 +2 if m = 0. +1 if low byte of dp register <> 0.	2

Pulls the status register and the program counter from the stack. On the 65c816 in native mode, also pulls the program bank register from the stack. Unlike the RTS instruction, the program counter address pulled off the stack is the exact address to return to. Pulling the status register gives the status flags the values they had immediately prior to the start of interrupt processing.

	STACK
stack pointer after RTI->	Old Status Register
	Return Address Bank
	Return Address High
	Return Address Low
stack pointer before RTI->
	BANK 0

Flag	Effect on Execution	Value after Execution
b
c		Restored to value prior to interrupt.
d		Restored to value prior to interrupt.
i		Restored to value prior to interrupt.
m		Restored to value prior to interrupt (65c816).
n		Restored to value prior to interrupt.
v		Restored to value prior to interrupt.
x		Restored to value prior to interrupt (65c816).
z		Restored to value prior to interrupt.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (rti)	RTI	65c02	$40	6 +1 on 65816 in native mode.	1

Pulls the program counter (incrementing the stacked, 16-bit value by one before loading the program counter with it), then the program bank register from the stack.

When a subroutine in another bank is called (via a jump to subroutine long instruction), the current bank address is pushed onto the stack along with the return address. To return to the calling bank, a long return instruction must be executed, which first pulls the return address from the stack and loads the program bank register. This transfer control to the instruction immediately following the original jump to subroutine long.

	STACK
stack pointer after RTI->	Return Address Bank
	Return Address High
	Return Address Low
stack pointer before RTI->
	BANK 0

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (rtl)	RTL	65c816	$6B	6	1

Pulls the program counter, incrementing the stacked, 16-bit value by one before loading the program counter with it.

When a subroutine is called (via a jump to subroutine instruction), the current address is pushed onto the stack. To return to the code following the subroutine call, a return instruction must be executed, which pulls the return address from the stack, increments it and loads the program counter with it, transferring control to the instruction immediately following the jump to subroutine.

	STACK
stack pointer after RTS->	Return Address High
	Return Address Low
stack pointer before RTS->
	BANK 0

Flag	Effect on Execution	Value after Execution
b
c
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
stack (rts)	RTS	65c02	$60	6	1

Subtracts the data located at the effective address specified by the operand from the contents of the accumulator. If the carry flag is clear, an additional 1 will be subtracted. The result is stored in the accumulator.

The 65x family of processors do not have a subtract instruction which does not use the carry flag. To avoid using the carry, make sure that it is set before the SBC instruction is executed. It can be explicitly set with SEC.

In a multi-word subtract, set the carry before the low words are subtracted. The low word subtraction then generates a new carry value for the subtraction of the next highest word, etc.

Flag	Effect on Execution	Value after Execution
b
c		0 = unsigned borrow required. 1 = unsigned borrow not required.
d	0 = binary subtraction. 1 = BCD subtraction.
i
m	0 = data subtracted is 16 bits. 1 and on 65c02 = data subtracted is 8 bits.
n		set to the most significant bit of the result.
v		0 = valid signed result. 1 = signed overflow.
x
z		0 = result is non-zero. 1 = result is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	SBC address	65c02	$ED	4 +1 if m=0.	3
absolute indexed, x	SBC address, X	65c02	$FD	4 +1 if m=0. +1 if adding index crosses page boundary.	3
absolute indexed, y	SBC address, Y	65c02	$F9	4 +1 if m=0. +1 if if adding index crosses page boundary.	3
absolute long	SBC long	65c816	$EF	5 +1 if m=0.	4
absolute long indexed, x	SBC long, X	65c816	$FF	5 +1 if m=0.	4
direct page (dp)	SBC dp	65c02	$E5	3 +1 if m=0. +1 if low byte of dp register <> 0.	2
dp indexed, x	SBC dp, X	65c02	$F5	6 +1 if m=0. +1 if low byte of dp register <> 0.	2
dp indexed indirect, x	SBC (dp, X)	65c02	$E1	6 +1 if m=0. +! if low order byte of dp register <> 0.	2
dp indirect indexed, y	SBC (dp), Y	65c02	$F1	5 +1 if m=0. +1 if low byte of dp register <> 0. +1 if adding index crosses page boundary.	2
dp indirect	SBC (dp)	65c02	$F2	5 +1 if m=0. +1 if low byte of dp register <> 0.	2
dp indirect long	SBC [dp]	65c816	$E7	6 +1 if m=0. +1 if low byte of dp register <> 0.	2
dp indirect long indexed, y	SBC [dp], Y	65c816	$F7	6 +1 if m=0. +1 if low byte of dp register <> 0.	2
immediate	SBC #const	65c02	$E9	2 +1 if m=0.	2 +1 if m=0.
sr indirect indexed, y	SBC (sr, S), Y	65c816	$F3	7 +1 if m=0.	2
stack relative (sr)	SBC sr, S	65c816	$E3	7 +1 if m=0.	2

Sets the carry flag in the status register. SEC can be used prior to subtraction to keep the carry flag from affecting the result. It is also used prior to the XCE instruction to put the 65c816 into 6502 emulation mode.

Flag	Effect on Execution	Value after Execution
b
c		sets the carry flag to 1.
d
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	SEC	65c02	$38	2	1

Set the decimal mode flag in the status register. This puts the processor into decimal mode from binary mode, so that the ADC and SBC instructions will operate correctly on BCD data and automatically perform decimal adjustment.

Flag	Effect on Execution	Value after Execution
b
c
d		set to 1.
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	SED	65c02	$F8	2	1

Set the interrupt disable flag in the status register. When the i bit is set, maskable hardware interrupts are ignored. The processor itself will set the i flag when it begins servicing an interrupt request. Thus, interrupt handling code should reenable interrupts with CLI if they are interruptible. If interrupts are to remain blocked during the execution of the interrupt handling code, exiting the routine via RTI will automatically restore the status register with the i flag clear, re-enabling interrupts.

Flag	Effect on Execution	Value after Execution
b
c
d
i		set to 1.
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	SEI	65c02	$78	2	1

This instruction takes a bit mask as an operand. Each bit that is set in the operand will cause the corresponding bit in the status register to set to 1. If a bit in the mask operand is 0, the corresponding bit in the status register remains unchanged.

7	6	5	4	3	2	1	0
n	v	m	x	d	i	z	c
negative	overflow	8 bit memory/accumulator	8 bit index registers	decimal	irq interrupt disable	zero result	carry

Flag	Effect on Execution	Value after Execution
c		1 = bit 0 is set in the SEP operand. otherwise, unchanged
d		1 = bit 3 is set in the SEP operand. otherwise, unchanged.
e	0 = all flags are modifiable. 1 = the break flag and bit 5 are unaffected by SEP.
i		1 = bit 2 is set in the SEP operand. otherwise, unchanged.
m		1 = bit 5 is set in the SEP operand. otherwise, unchanged.
n		1 = bit 7 is set in the SEP operand. otherwise, unchanged.
v		1 = bit 6 is set in the SEP operand. otherwise, unchanged.
x		1 = bit 4 is set in the SEP operand. otherwise, unchanged.
z		1 = bit 1 is set in the SEP operand. otherwise, unchanged.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
immediate	SEP #const	65c816	$E2	3	2

Store the value in the accumulator to the effective address specified by the operand.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m	0 = data is 16 bits. 1 and on 65c02 = data is 8 bits.
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	STA addr	65c02	$8D	4 +1 if m = 0.	3
absolute indexed, x	STA addr, X	65c02	$9D	5 +1 if m = 0.	3
absolute indexed, y	STA addr, Y	65c02	$99	5 +1 if m = 0.	3
absolute long	STA long	65c816	$8F	5 +1 if m = 0.	4
absolute long indexed, x	STA long, X	65c816	$9F	5 +1 if m = 0.	4
direct page (dp)	STA dp	65c02	$85	3 +1 if m = 0. +1 if low byte of direct page register <> 0.	2
dp indexed, x	STA dp, X	65c02	$95	4 +1 if m = 0. +1 if low byte of direct page register <> 0.	2
dp indexed indirect, x	STA (dp, X)	65c02	$81	6 +1 if m = 0. +1 if low byte of direct page register <> 0.	2
dp indirect	STA (dp)	65c02	$92	5 +1 if m = 0. +1 if low byte of direct page register <> 0.	2
dp indirect indexed, y	STA (dp), Y	65c02	$91	6 +1 if m = 0. +1 if low byte of direct page register <> 0.	2
dp indirect long	STA [dp]	65c816	$87	6 +1 if m = 0. +1 if low byte of direct page register <> 0.	2
dp indirect long indexed, y	STA [dp], Y	65c816	$97	6 +1 if m = 0. +1 if low byte of direct page register <> 0.	2
stack relative (sr)	STA sr, s	65c816	$83	4 +1 if m = 0.	2
stack indirect indexed, y	STA (sr, S), Y	65c816	$93	7 +1 if m = 0.	2

During the processor’s next phase 2 clock cycle, stops the processor’s oscillator input. The processor is effectively shut down until a reset occurs (/RES pin is pulled low).

This is designed to put the processor to sleep while it’s not actively in use, in order to reduce power consumption.

The reset handling routine ($00:FFFC-$00:FFFD) should be designed to either reinitialize the system or resume control though a previously-installed reset handler.

Reset is an interrupt-like signal that causes the emulation bit to be set to one. It also causes the direct page register to reset to 0, stack high to set to one (forcing the stack page pointer to page one) and the mode select flags to be set to one (8-bit registers, so the high bytes of the index registers are zeroed).

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	STP	65c816	$DB	3 3 cycles to shut the processor down. additional cycles are required by reset to restart it.	1

Store the value in the index register X to the effective address specified by the operand.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n
v
x	0 = data is 16 bits. 1 and on 65c02 = data is 8 bits.
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	STX addr	65c02	$8E	4 +1 if x = 0.	3
direct page	STX dp	65c02	$86	3 +1 if x = 0. +1 if low byre of direct page register <> 0.	2
direct page indexed, y	STX dp, Y	65c02	$96	4 +1 if x = 0. +1 if low byte of direct page register <> 0.	2

Store the value in the index register Y to the effective address specified by the operand.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n
v
x	0 = data is 16 bits. 1 and on 65c02 = data is 8 bits.
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	STX addr	65c02	$8C	4 +1 if x = 0.	3
direct page	STX dp	65c02	$84	3 +1 if x = 0. +1 if low byre of direct page register <> 0.	2
direct page indexed, x	STX dp, X	65c02	$94	4 +1 if x = 0. +1 if low byte of direct page register <> 0.	2

Stores 0 to the effective address specified by the operand.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m	0 = data is 16 bits. 1 and on 65c02 = data is 8 bits.
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	STZ addr	65c02	$9C	4 +1 if m = 0.	3
absolute indexed, x	STZ addr, X	65c02	$9E	5 +1 if m = 0.	3
direct page	STZ dp	65c02	$64	3 +1 if m = 0. +1 if low byre of direct page register <> 0.	2
direct page indexed, x	STZ dp, X	65c02	$74	4 +1 if m = 0. +1 if low byte of direct page register <> 0.	2

B represents the high-order byte of the 16 bit C accumulator, and A in this case represents the low-order byte. XBA swaps the contents of the low-order and high-order bytes of C.

An alternate mnemonic is XBA (Exchange the B and A accumulators).

SWA can be used to invert the low-order, high-order arrangement of a 16-bit value, or to temporarily store an 8-bit value from the A accumulator into B. Since it is an exchange, the previous contents of both accumulators are changed, replaced by the previous contents of the other.

Neither mode select flags nor the emulation mode flag affects this operation.

The flags are changed based on the new value of the low byte the A accumulator (that is, on the former value of the high byte, the B accumulator), even in 16 bit accumulator mode.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		set to the most significant bit of the value that is transferred from the B accumulator to the A accumulator.
v
x
z		0 = 8 bit value transferred to A accumulator is non-zero. 1 = 8 bit value transferred to A accumulator is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	SWA (or XBA)	65c816	$EB	3	1

Transfers the value in the 16-bit accumulator (A) to the Direct Page register D, regardless of the setting of the accumulator/memory mode flag.

An Alternate mnemonic is TCD (Transfer C accumulator to Direct Page register).

If the A accumulator is set to just eight bits (whether because of the m flag or because the processor is in 6502 emulation mode), then its value becomes the low byte of the Direct Page register and the value in the hidden B accumulator becomes the high byte of the Direct Page register.

The accumulator’s 16 bit value is unchanged by the operation.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		Set to the most significant bit of the transferred value.
v
x
z		0 = transferred value <> 0. 1 = transferred value == 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TAD (or TCD)	65c816	$5B	2	1

Transfers the value of the accumulator to the Stack Pointer S. The accumulator’s value is unchanged.

An alternate mnemonic is TCS (Transfer C accumulator to Stack Pointer register).

If the A accumulator is set to just eight bits (whether because of the m flag or because the processor is in 6502 emulation mode), then its value becomes the low byte of the Stack Pointer register and the value in the hidden B accumulator becomes the high byte of the Stack Pointer register.

The accumulator’s 16 bit value is unchanged by the operation.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		Set to the most significant bit of the transferred value.
v
x
z		0 = transferred value <> 0. 1 = transferred value == 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TAS (or TCS)	65c816	$1B	2	1

Transfers the value in the accumulator to the index register X. If the registers are different sizes, the nature of the transfer is determined by the X register. TAX does not change the value in the accumulator.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		most significant bit of the value transferred.
v
x	0 = value transferred is 16 bits. 1 = the lower 8 bits of the accumulator are transferred.
z		0 = result in x <> 0. 1 = result in x == 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TAX	65c02	$AA	2	1

Transfers the value in the accumulator to the index register Y. If the registers are different sizes, the nature of the transfer is determined by the Y register. TAY does not change the value in the accumulator.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		most significant bit of the value transferred.
v
x	0 = value transferred is 16 bits. 1 = the lower 8 bits of the accumulator are transferred.
z		0 = result in y <> 0. 1 = result in y == 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TAY	65c02	$A8	2	1

Transfers the value in the 16-bit accumulator (C) to the Direct Page register D, regardless of the setting of the accumulator/memory mode flag.

An Alternate mnemonic is TAD (Transfer A accumulator to Direct Register).

If the A accumulator is set to just eight bits (whether because of the m flag or because the processor is in 6502 emulation mode), then its value becomes the low byte of the Direct Page register and the value in the hidden B accumulator becomes the high byte of the Direct Page register.

The accumulator’s 16 bit value is unchanged by the operation.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		Set to the most significant bit of the transferred value.
v
x
z		0 = transferred value <> 0. 1 = transferred value == 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TCD (or TAD)	65c816	$5B	2	1

Transfers the value of the accumulator to the Stack Pointer S. The accumulator’s value is unchanged.

An alternate mnemonic is TAS (Transfer A accumulator to Stack Pointer register).

If the A accumulator is set to just eight bits (whether because of the m flag or because the processor is in 6502 emulation mode), then its value becomes the low byte of the Stack Pointer register and the value in the hidden B accumulator becomes the high byte of the Stack Pointer register.

The accumulator’s 16 bit value is unchanged by the operation.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		Set to the most significant bit of the transferred value.
v
x
z		0 = transferred value <> 0. 1 = transferred value == 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TCS (or TAS)	65c816	$1B	2	1

Transfers the value in the 16-bit Direct Page register D to the 16-bit Accumulator C, regardless of the setting of the accumulator/memory mode flag.

An alternate mnemonic is TDC (Transfer Direct Page register to C Accumulator).

If the A accumulator is set to just 8 bits (whether because the m flag is set, or because the processor is in 6502 emulation mode), then it takes the value of the low byte of the Direct Page register and the hidden B accumulator takes the value of the high byte of the Direct Page register.

The Direct Page register’s 16-bit value is unchanged.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		the most significant bit of the transferred value.
v
x
z		0 = transferred value <> 0. 1 = transferred value == 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TDA (or TDC)	65c816	$7B	2	1

Transfers the value in the 16-bit Direct Page register D to the 16-bit Accumulator C, regardless of the setting of the accumulator/memory mode flag.

An alternate mnemonic is TDA (Transfer Direct Page register to A Accumulator).

If the A accumulator is set to just 8 bits (whether because the m flag is set, or because the processor is in 6502 emulation mode), then it takes the value of the low byte of the Direct Page register and the hidden B accumulator takes the value of the high byte of the Direct Page register.

The Direct Page register’s 16-bit value is unchanged.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		the most significant bit of the transferred value.
v
x
z		0 = transferred value <> 0. 1 = transferred value == 0.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TDC (or TDA)	65c816	$7B	2	1

Logically “AND” together the complement of the value in the accumulator with the data at the effective address specified by the operand. Stores the result at the memory location.

This has the effect of clearing each memory bit for which the corresponding accumulator bit is set, while leaving unchanged all memory bits in which the corresponding accumulator bits are zeroes.

Unlike the BIT instruction, TRB is a read-modify-write instruction, not only calculating a result and modifying a flag, but also storing the result to memory.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n
v
x
z		0 = memory value AND’ed with accumulator value is nonzero. 1 = memory value AND’ed with accumulator value is zero

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	TRB addr	65c02	$1C	6 +1 if m = 0.	3
direct page (dp)	TRB dp	65c02	$14	5 +1 if m = 0. +1 if low byte of dp register <> 0.	2

Transfer the value in the 16-bit Stack Pointer S to the 16-bit accumulator A, regardless of the setting of the accumulator/memory mode flag.

An alternate mnemonic is TSC (Transfer the value in the Stack Pointer register to C accumulator).

If the A accumulator is set to just 8 bits (whether because the m flag is set or because the processor is in 6502 emulation mode), then it takes the value of the low byte of the stack pointer and the hidden B accumulator takes the value of the high byte of the stack pointer. In emulation mode, B will always take a value of one, since the stack is confined to page one.

The stack pointer’s value is unchanged.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		set to the most significant bit of the transferred value.
v
x
z		0 = the transferred value is nonzero. 1 = the transferred value is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TSA (or TSC)	65c816	$3B	2	1

Logically “OR” together the value in the accumulator with the data at the effective address specified by the operand. Store the result at the memory location.

This has the effect of setting each memory bit for which the corresponding accumulator bit is set, while leaving unchanged all memory bits in which the corresponding accumulator bits are zeroes.

Unlike the BIT instruction, TSB is a read-modify-write instruction, not only calculating a result and modifying a flag, but storing the result to memory.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n
v
x
z		0 = memory AND’ed with accumulator value is nonzero 1 = memory AND’ed with accumulator value is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
absolute	TSB addr	65c02	$0C	6 +1 if m = 0.	3
direct page	TSB dp	65c02	$04	5 +1 if m = 0. +1 if low byte of direct page register <> 0.	2

Transfer the value in the 16-bit Stack Pointer S to the 16-bit accumulator C, regardless of the setting of the accumulator/memory mode flag.

An alternate mnemonic is TSA (Transfer the value in the Stack Pointer register to Accumulator).

If the A accumulator is set to just 8 bits (whether because the m flag is set or because the processor is in 6502 emulation mode), then it takes the value of the low byte of the stack pointer and the hidden B accumulator takes the value of the high byte of the stack pointer. In emulation mode, B will always take a value of one, since the stack is confined to page one.

The stack pointer’s value is unchanged.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		set to the most significant bit of the transferred value.
v
x
z		0 = the transferred value is nonzero. 1 = the transferred value is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TSC (or TSA)	65c816	$3B	2	1

Transfers the value in the Stack Pointer S to the index register X. The Stack Pointer’s value is not changed.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		n is set to the most significant bit of the transferred value
v
x	0 = the full 16 bit value in the stack pointer is transferred to the x register. 1 and 65c02 = only the low byte of the value in the stack pointer is transferred to the x register.
z		0 = the transferred value is nonzero 1 = the transferred value is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TSX	65c02	$BA	2	1

Transfer the value in index register X to the accumulator. If the registers are different sizes, the nature of the transfer is determined by the destination (accumulator). The value in the index register is not changed by the operation.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m	0 = if the index register is 8 bits, those 8 bits are transferred to the low byte of the accumulator and the upper 8 bits are zeroed. if the index register is 16 bits, it is copied to the accumulator. 1 = if the index register is 8 bits, it is copied to the accumulator. if the index register is 16 bits, the lower 8 bits are stored in the accumulator and the upper 8 bits are ignored, the hidden B accumulator is not changed.
n		set to the value of the most significant bit of the transferred value
v
x
z		0 = transferred value is nonzero. 1 = transferred value is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TXA	65c02	$8A	2	1

Transfer the value in index register X to the Stack Pointer S. The index register’s value is not changed by the operation.

TXS, along with TCS are the only two instructions for changing the value in the Stack Pointer. The two are also the only two transfer instructions that do not alter the flags.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n
v
x	0 = the full 16 bit value in x is transferred to the stack pointer. 1 = the 8bit x register is transferred to the lower byte of the stack pointer. the upper byte of the stack pointer is zeroed.
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TXS	65c02	$9A	2	1

Transfers the value in index register X to index register Y. The value in index register X is not changed.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		set to the most significant bit of the transferred value.
v
x	0 = value transferred is 16 bits. 1 and 6502 = value transferred is 8 bits.
z		0 = transferred value is nonzero. 1 = transferred value is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TXY	65c816	$9B	2	1

Transfers the value in index register Y to the accumulator. If the registers are different sizes, the nature of the transfer is determined by the destination (accumulator). The value in the index register is not changed.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m	0 = if x = 0, then the 16 bit contents of y are copied to the 16 bit accumulator. if x = 1 then the 8 bit index register is copied to the low byte of the accumulator and the high byte of the accumulator is zeroed. 1 = if x = 0, then the lower 8 bits of the 16 bit y are copied to the 8 bit accumulator. if x = 1 then the 8 bit y is copied to the 9 bit accumulator.
n		set to the most significant bit of the transferred value.
v
x
z		0 = transferred value is nonzero. 1 = transferred value is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TYA	65c02	$98	2	1

Transfers the value in index register Y to index register X. The value in index register Y is unchanged. Note that X and Y are never different sizes.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		set to the most significant bit of the transferred value.
v
x
z		0 = transferred value is nonzero. 1 = transferred value is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	TYX	65c816	$BB	2	1

Pulls the RDY pin low. Power consumption is reduced and RDY remains low until an external hardware interrupt is received (NMI, IRQ, ABORT or RESET).

WAI is designed to put the processor to sleep during an external event to reduce its power consumption, to allow it to be synchronized with an external event, and/or to reduce interrupt latency (an interrupt occurring during execution of an instruction is not acted upon until execution of the instruction is complete, perhaps many cycles later; WAIT ensures that an interrupt is recognized immediately).

Once an interrupt is received, control is vectored through one of the hardware interrupt vectors; an RTI from the interrupt handling routine will return control to the instruction following the original WAI. However, if by setting the i flag, interrupts have been disabled prior to the execution of the WAI instruction, and IRQ’ is asserted, the “wait” condition is terminated and control resumes with the next instruction, rather than through the interrupt vectors. This provides the quickest response to an interrupt, allowing synchronization with external events. WAI also frees up the bus; since RDY is pulled low in the third instruction cycle, the processor may be disconnected from the bus if BE is also pulled low.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	WAI	65c816	$CB	3 +additional cycles required by interrupt to restart the processor.	1

This instruction was provided for future expansion of the instruction set to 16 bit opcodes. This opcode would signal that another instruction byte follows which would be an opcode in the expanded instruction set. It was given the temporary mnemonic WDM which are the initials of the processors’ designer, William D. Mensch, Jr.

WDM shouldn’t be used in a program, as it would introduce incompatibilities with possible future 65x processors. If it accidentally executed, it will act like a two-byte NOP instruction.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n
v
x
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
	WDM	65c816	$42	?	2?

B represents the high-order byte of the 16 bit C accumulator, and A in this case represents the low-order byte. XBA swaps the contents of the low-order and high-order bytes of C.

An alternate mnemonic is SWA (Swap the high and low bytes of the 16-bit A Accumulator).

XBA can be used to invert the low-order, high-order arrangement of a 16-bit value, or to temporarily store an 8-bit value from the A accumulator into B. Since it is an exchange, the previous contents of both accumulators are changed, replaced by the previous contents of the other.

Neither mode select flags nor the emulation mode flag affects this operation.

The flags are changed based on the new value of the low byte the A accumulator (that is, on the former value of the high byte, the B accumulator), even in 16 bit accumulator mode.

Flag	Effect on Execution	Value after Execution
c
d
e
i
m
n		set to the most significant bit of the value that is transferred from the B accumulator to the A accumulator.
v
x
z		0 = 8 bit value transferred to A accumulator is non-zero. 1 = 8 bit value transferred to A accumulator is zero.

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	XBA (or SWA)	65c816	$EB	3	1

This instruction is the only means provided by the 65c816 to shift between 65c02 emulation mode and the full, 16-bit native mode.

The emulation mode is used to provide hardware and software compatibility between the 65c02 and 65c816.

If the processor is in emulation mode, then to switch to native mode, first clear the carry bit, then execute an XCE. Since it is an exchange operation, the carry flag will reflect the previous state of the emulation bit. Switching to native mode causes bit five to stop functioning as the break flag, and function instead as the x mode select flag. A second mode select flag, m, uses bit six, which was unused in emulation mode. Both mode select flags are initially set to one (eight-bit modes). There are also other differences described in the text.

If the processor is in native mode, then to switch to emulation mode, you first set the carry bit, then execute an XCE. Switching to emulation mode causes the mode select flags (m and x) to be lost from the status register, with x replaced by the b break flag. This forces the accumulator to eight bits, but the high accumulator byte is preserved in the hidden B accumulator. It also forces the index registers to eight bits, causing the loss of values in their high bytes, and the stack to page one, causing the loss of the high byte of the previous stack address. There are also other differences described in the text

Flag	Effect on Execution	Value after Execution
c		takes emulation (e flag) bit’s previous value.
d
e		takes carry (c flag) bit’s previous value.
i
m		1
n
v
x		1
z

Addressing	Syntax	Processor	OpCode	Cycles	Bytes
implied	XCE	65c816	$FB	2	1