65C816 Instruction Set

Mnemonics are listed alphabetically. Instructions marked with “*” are particular to the 65C816, the rest are also present on the 65C02. The table layout and arrangement is for presentation only. For the most part, “65C816” also applies to the 65c802.

References: 65c02 and 65c816 datasheets, “Programming the 65816: including the 6502, 65c02, and 65802” by David Eyes and Ron Lichty.

ADCANDASL
BCCBCSBEQBITBMIBNEBPLBRABRKBRLBVCBVS
CLCCLDCLICLVCMPCOP*CPXCPY
DECDEXDEY
EOR
INCINXINY
JML*JMPJSL*JSR
LDALDXLDYLSR
MVN*MVP*
NOP
ORA
PEA*PEI*PER*PHAPHB*PHD*PHK*PHPPHXPHYPLAPLBPLD*PLPPLXPLY
REP*ROLRORRTIRTL*RTS
SBCSECSEDSEISEP*STASTPSTXSTYSTZSWA*
TAD*TAS*TAXTAYTCD*TCS*TDA*TDC*TRBTSA*TSBTSC*TSXTXATXSTXYTYATYX*
WAIWDM*
XBA*XCE*

ADC

Add memory to accumulator with carry.

Adds the data located at the effective address specified by the operand to the contents of the accumulator. If the carry flag is set, another 1 is added to the accumulator. The final result is stored in the accumulator.

FlagEffect on ExecutionValue after Execution
c1 = 1 is added to the result of the addition of the referenced value to the accumulator.0 = valid unsigned result.
1 = unsigned overflow
d0 = Binary addition is performed.
1 = BCD addition is performed.
i
m0 = 16 bit accumulator, data from memory is 16 bits, with the low byte at the operand address and the high byte at the next address. 65c816 only.
1 = 8 bit accumulator, data from memory is 8 bits.
nset to most significant bit of result
v0 = valid signed result
1 = signed overflow
x
z0 = result is nonzero
1 = result is zero
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteADC addr65c02$6D4
+1 if m=0
+1 if 65c02 and d=1
3
absolute indexed, xADC addr, X65c02$7D4
+1 if page crossed
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
3
absolute indexed, yADC addr, Y65c02$794
+1 if page crossed
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
3
absolute longADC long65c816$6F5
+1 if m=0
4
absolute long indexed, xADC long, X65c816$7F5
+1 if m=0
4
direct page (dp)ADC dp65c02$653
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
stack relativeADC sr, S65c816$634
+1 if m=0
2
dp indexed, xADC dp, X65c02$754
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
dp indirectADC (dp)65c02$725
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
dp indirect longADC [dp]65c816$676
+1 if m=0
+1 if low byte of dp register is nonzero
2
sr indirect indexed, yADC (sr, S), Y65c816$737
+1 if m=0
2
dp indexed indirect, xADC (dp, X)65c02$616
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
dp indirect indexed, yADC (dp, Y)65c02$715
+1 if page crossed
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
+1 if low byte of dp register is nonzero
2
dp indirect long indexed, yADC [dp], Y65c816$776
+1 if m=0
+1 if low byte of dp register is nonzero
2
immediateADC #const65c02$692
+1 if m=0
+1 if 65c02 and d=1
2
+1 if m=0
Valid addressing modes.

AND

“AND” memory with accumulator.

Bitwise logical AND the data at the effective address specified by the operand with the contents of the accumulator. The final result is stored in the accumulator.

FlagEffect on ExecutionValue after Execution
c
d
i
m0 = 16 bit accumulator, data from memory is 16 bits, with the low byte at the operand address and the high byte at the next address. 65c816 only.
1 = 8 bit accumulator, data from memory is 8 bits.
nset to most significant bit of result
v
x
z0 = result is nonzero
1 = result is zero
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteAND addr65c02$2D4
+1 if m=0
3
absolute indexed, xAND addr, X65c02$3D4
+1 if m=0
+1 if adding index crosses page boundary
3
absolute indexed, yAND addr, Y65c02$394
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
3
absolute longAND long65c816$2F5
+1 if m=0
4
absolute long indexed, xAND long, X65c816$3F5
+1 if m=0
4
direct page (dp)AND dp65c02$253
+1 if m=0
+1 if low byte of dp register is nonzero
2
stack relativeAND sr, S65c816$234
+1 if m=0
2
dp indexed, xAND dp, X65c02$354
+1 if m=0
+1 if low byte of dp register is nonzero
2
dp indirectAND (dp)65c02$325
+1 if m=0
+1 if low byte of dp register is nonzero
2
dp indirect longAND [dp]65c816$276
+1 if m=0
+1 if low byte of dp register is nonzero
2
sr indirect indexed, yAND (sr, S), Y65c816$237
+1 if m=0
2
dp indexed indirect, xAND (dp, X)65c02$216
+1 if m=0
+1 if low byte of dp register is nonzero
2
dp indirect indexed, yAND (dp, Y)65c02$315
+1 if m=0
+1 if adding index crosses page boundary
+1 if low byte of dp register is nonzero
2
dp indirect long indexed, yAND [dp], Y65c816$376
+1 if m=0
+1 if low byte of dp register is nonzero
2
immediateAND #const65c02$292
+1 if m=0
2
+1 if m=0
Valid addressing modes.

ASL

Shift memory or accumulator one bit left.

Shift the contents of the location specified by the operand left one bit. The most significant bit is transferred into the carry flag, while the least significant bit is cleared. This effectively multiplies the value by two.

FlagEffect on ExecutionValue after Execution
cHigh bit is shifted into carry.
d
i
m0 = 16 bit accumulator, data from memory is 16 bits, with the low byte at the operand address and the high byte at the next address. 65c816 only.
1 = 8 bit accumulator, data from memory is 8 bits.
nset to most significant bit of result
v
x
z0 = result is nonzero
1 = result is zero
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
accumulatorASL A65c02$0A21
absoluteASL addr65c02$0E6
+1 if m=0
3
absolute indexed, xASL addr, X65c02$1E7
+1 if m=0
-1 if 65c02 and no page boundary crossed
3
direct page (dp)ASL dp65c02$065
+1 if m=0
+1 if low byte of dp register is nonzero
2
dp indexed, xASL dp, X65c02$352
+1 if m=0
+1 if low byte of dp register is nonzero
6
Valid addressing modes.

BCC

Branch on carry clear (c = 0).

The carry flag is tested and, if it is clear, a branch is taken. If it is set, execution continues with the instruction immediately following the two-byte BCC instruction.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

After a comparison or subtraction, if the accumulator is less than the operand, BCC will branch.

FlagEffect on ExecutionValue after Execution
cInstruction will branch if c = 0, it will fall through to the next instruction if c = 1.
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relativeBCC offset65c02$902
+1 if branch taken
+1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1
2
Valid addressing modes.

BCS

Branch on carry set (c = 1).

The carry flag is tested and, if set, a branch is taken. If it is clear, the instruction immediately following the two-byte BCS instruction is executed.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

After a comparison or subtraction, if the accumulator is greater than or equal to the operand, BCS will branch.

FlagEffect on ExecutionValue after Execution
cInstruction will branch if c = 1, it will fall through to the next instruction if c = 0.
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relativeBCS offset65c02$B02
+1 if branch taken
+1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1
2
Valid addressing modes.

BEQ

Branch if equal (z = 1).

The zero flag is tested. If it is set, a branch is taken. If it is clear, the instruction immediately following the two-byte BEQ is executed.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

After a comparison or subtraction, if the accumulator is equal to the operand, or if an instruction results in 0, such as a decrement from one, BEQ will branch.

FlagEffect on ExecutionValue after Execution
c
d
i
m
n
v
x
zInstruction will branch if z = 1, it will fall through to the next instruction if z = 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relativeBEQ offset65c02$F02
+1 if branch taken
+1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1
2
Valid addressing modes.

BIT

Test memory bits against the accumulator.

Sets the status register flags based on the result of two different operations:

  1. Sets or clears the n flag to reflect the value of the high bit of the data located at the effective address specified by the operand, and sets or clears the v flag to reflect the contents of the next-to-highest bit of the data addressed.
  2. Logically ANDs the data located at the effective address with the contents of the accumulator; it changes neither value, but sets the z flag if the result is zero, or clears it if the result is non-zero.

BIT is usually used immediately preceding a conditional branch instruction: to test a memory value’s highest or next-to-highest bits; with a mask in the accumulator, to test any bits of the memory operand; or with a constant as the mask (using immediate addressing) or a mask in memory, to test any bits in the accumulator. All of these tests are non-destructive of the data in the accumulator or in memory. When the BIT instruction is used with the immediate addressing mode, the n and v flags are unaffected.

FlagEffect on ExecutionValue after Execution
c
d
i
m0 = 16 bit accumulator, data from memory is 16 bits, with the low byte at the operand address and the high byte at the next address. 65c816 only. Bit 15 is moved into the n flag and bit 14 is moved into the v flag.
1 = 8 bit accumulator, data from memory is 8 bits.
nValue of most significant bit of memory data.
vValue of next-most-significant bit of memory data.
x
z1 = logical AND of memory and accumulator is zero, 0 = logical AND of memory and accumulator <> 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteBIT add65c02$2C2
+1 if m = 0
2
+1 if m = 0
absolute indexed, xBIT add, X65c02$3c4
+1 if m = 0
+1 if adding index crosses page boundary
3
direct page (dp)BIT dp65c02$244
+1 if m = 0
+1 if low byte of dp register <> 0
3
dp indexed, xBIT dp, X65c02$344
+1 if m = 0
+1 if low byte of dp register <> 0
2
immediateBIT #const65c02$892
+1 if m = 0
2
+1 if m = 0
Valid addressing modes.

BMI

Branch if result minus (n = 1).

The negative flag is tested. If it is set, the branch is taken. A number with its high bit set may be interpreted as a negative twos-complement number, so this instruction tests, among other things, for the sign of two’s-complement numbers. If the negative flag is clear, the instruction immediately following the two-byte BMI instruction is executed.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

FlagEffect on ExecutionValue after Execution
c
d
i
m
nbranches if n = 1, continues with the next instruction after the BMI if n = 0
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relativeBMI offset65c02$302
+1 if branch taken
+1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1
2
Valid addressing modes.

BNE

Branch if not equal (z = 0).

The zero flag is tested. If it is clear, a branch is taken. If it is set, the instruction immediately following the two-byte BNE is executed.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

After a comparison or subtraction, if the accumulator is not equal to the operand, or if an instruction results in a non-zero, such as an increment from zero, BNE will branch.

FlagEffect on ExecutionValue after Execution
c
d
i
m
n
v
x
zInstruction will branch if z = 0, it will fall through to the next instruction if z = 1.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relativeBNE offset65c02$D02
+1 if branch taken
+1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1
2
Valid addressing modes.

BPL

Branch if result plus (n = 0).

The negative flag is tested. If it is clear, a branch is taken. In the two’s-complement system, values with their high byte clear are interpreted as positive numbers. If the flag is set, the branch is not taken and the instruction following the two-byte BPL is executed. In two’s-complement, this means the number was negative.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

FlagEffect on ExecutionValue after Execution
c
d
i
m
n0 = branch is taken
1 = branch is not taken, next instruction is executed.
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relativeBPL offset65c02$102
+1 if branch taken
+1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1
2
Valid addressing modes.

BRA

Branch always.

This is similar to an unconditional JMP, but with signed displacements instead of absolute addresses. This makes this instruction relocatable.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

FlagEffect on ExecutionValue after Execution
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relativeBRA offset65c02$803
+1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1
2
Valid addressing modes.

BRK

Force break.

Force a software interrupt. BRK is unaffected by the interrupt disable flag. Although BRK is a one-byte instruction, the program counter (which is pushed onto the stack by the instruction) is incremented by two. This lets you follow the break instruction with a signature byte indicating which break caused the interrupt. This byte must always be present, even if not used, OR the return address on the stack decremented to account for its absence and allow the RTI to work properly.

On the 65c02 and in 65c816 emulation mode, the program counter is incremented by two, then pushed onto the stack; the status register, with the b break flag set, is pushed onto the stack; the interrupt disable flag is set; and the program counter is loaded from the interrupt vector at $FFFE-FFFF.

It is up to the interrupt handling routine at this address to check the b flag in the stacked status register to determine if the interrupt was caused by a software interrupt (BRK) or by a hardware IRQ, which shares the BRK vector but pushes the status register onto the stack with the b break flag clear. For example:

PLA       ; copy status from top of stack
PHA
AND #$10  ; check brk bit
BNE IsBRK ; branch if set

On the 65c816, the program counter bank register is pushed onto the stack; the program counter is incremented by two and pushed onto the stack; the status register is pushed onto the stack; the interrupt disable flag is set; the program bank register is cleared to zero; and the program counter is loaded from the break vector at $OOFFE6-OOFFE7.

FlagEffect on ExecutionValue after Execution
bon the 65c02 and 65c816 in emulation mode, set when pushed onto the stack before calling the interrupt service routine.
c
dreset to 0 after BRK is executed.
iset to 1, disabling hardware IRQs
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack/interruptBRK65c02$007
+1 if 65816 if e = 0
2
instruction is 1 byte, but program counter value pushed onto the stack is incremented by 2 allowing for signature byte
Valid addressing modes.

BRL*

Branch always long.

Similarly to BRA, this instruction always branches. Unlike BRA, the displacement is a signed 16 bit value, not a signed 8 bit value. The allowable range of the displacement is anywhere within the current 64K program bank. This is a relocatable branch instruction.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relative longBRL label65c816$8243
Valid addressing modes.

BVC

Branch on overflow clear (v = 0).

This instruction branches if the overflow flag is clear. If the overflow flag is set, the next instruction after the two-byte BVC is executed. The overflow flag is altered by only four instructions on the 65c02: addition, subtraction, CLV and BIT and two further instructions, SEP and REP on the 65816. The flag can also be set by a hardware pin on the processor.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v0 = instruction will branch
1 = instruction will not branch
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relativeBVC offset65c02$502
+1 if branch taken
+1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1
2
Valid addressing modes.

BVS

Branch on overflow set (v = 1).

This instruction branches if the overflow flag is set. If it is clear, the next instruction following the two-byte BVS is executed. The overflow flag is altered by only four instructions on the 65c02: addition, subtraction, CLV and BIT and two further instructions, SEP and REP on the 65816. The flag can also be set by a hardware pin on the processor. BVS is used almost exclusively to determine if a two’s-complement arithmetic calculation has overflowed, much as the carry is used to determine if an unsigned arithmetic calculation has overflowed. (Note, however, that the compare instructions do not affect the overflow flag.) You can also use BVS to test the second-highest bit in a value by using it after the BIT instruction, which moves the second-highest bit of the tested value into the v flag.

The second byte of the instruction is a one-byte sign-extended displacement that is added to the program counter if the branch is taken. Control resumes from that new address. The maximum displacement is -128 to +127, calculated from the instruction immediately following the branch.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v0 = instruction will not branch
1 = instruction will branch
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
program counter relativeBVS offset65c02$702
+1 if branch taken
+1 if branch taken crosses a page boundary on 65c02 or 65816 if e = 1
2
Valid addressing modes.

CLC

Clear the carry flag.

This instruction can be used prior to an addition to prevent the carry flag from affecting the result. Used prior to BCC, it will force a branch and on the 65816, it is used along with XCE to put the 65816 into emulation mode.

FlagEffect on ExecutionValue after Execution
b
c0
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedCLC65c02$1821
Valid addressing modes.

CLD

Turn off decimal mode (clear the d flag).

This instruction clears the d flag, which turns off Binary Coded Decimal mode. Use this when ADC and SBC need to operate on binary data rather than BCD data.

FlagEffect on ExecutionValue after Execution
b
c
d0
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedCLD65c02$D821
Valid addressing modes.

CLI

Clear interrupt disable bit. Enables interrupts.

Clears the interrupt disable bit in the flags register. This enables interrupt handling. The processor sets the interrupt disable flag when an interrupt service routine is called and restores it when the subsequent RTI instruction is executed.

FlagEffect on ExecutionValue after Execution
b
c
d
i0
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedCLI65c02$5821
Valid addressing modes.

CLV

Clear the overflow flag.

Clears the overflow flag. There is no instruction to explicitly set the overflow flag. This can be accomplished through hardware via the Set Overflow pin, as can a BIT instruction with bit 6 set.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v0
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedCLV65c02$B821
Valid addressing modes.

CMP

Compare memory and accumulator.

Compares the data referenced by the parameter to the contents of the accumulator. This is an internal subtraction operation where the data is subtracted from the accumulator and the processor flags are set accordingly. The result of the subtraction is discarded, neither the referenced data nor the accumulator are changed. Note also that the value of the carry flag is not used in the operation and the overflow flag is not set, this means CMP only good for unsigned comparisons.

FlagEffect on ExecutionValue after Execution
b
c1 = no borrow required (accumulator >= data).
0 = borrow required (accumulator < data).
d
i
m0 = comparison is 16 bits on 65816.
1 = comparison is 8 bits on 65816.
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteADC addr65c02$6D4
+1 if m=0
+1 if 65c02 and d=1
3
absolute indexed, xADC addr, X65c02$7D4
+1 if page crossed
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
3
absolute indexed, yADC addr, Y65c02$794
+1 if page crossed
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
3
absolute longADC long65c816$6F5
+1 if m=0
4
absolute long indexed, xADC long, X65c816$7F5
+1 if m=0
4
direct page (dp)ADC dp65c02$653
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
stack relativeADC sr, S65c816$634
+1 if m=0
2
dp indexed, xADC dp, X65c02$754
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
dp indirectADC (dp)65c02$725
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
dp indirect longADC [dp]65c816$676
+1 if m=0
+1 if low byte of dp register is nonzero
2
sr indirect indexed, yADC (sr, S), Y65c816$737
+1 if m=0
2
dp indexed indirect, xADC (dp, X)65c02$616
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
dp indirect indexed, yADC (dp, Y)65c02$715
+1 if page crossed
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
+1 if low byte of dp register is nonzero
2
dp indirect long indexed, yADC [dp], Y65c816$776
+1 if m=0
+1 if low byte of dp register is nonzero
2
immediateADC #const65c02$692
+1 if m=0
+1 if 65c02 and d=1
2
+1 if m=0
Valid addressing modes.

COP*

Coprocessor enable.

This instruction generates a software interrupt that jumps to a COP vector ($FFF4, $FFF5) and is unaffected by the interrupt disable flag, i. COP may also be trapped by a co-processor. As with BRK, the COP instruction increments the program counter by two, providing a byte after the opcode to use as an identifier. Identifiers in the range $80 to $FF are reserved by Western Design Center. Identifiers in the range $00 to $79 are available for use by software interrupt handlers.

FlagEffect on ExecutionValue after Execution
b
c
d0 – decimal mode is disabled.
e0 = pc incremented by 2 and pushed onto stack, status register pushed on stack, irq disable flag set, pc is loaded from $fff4, $fff5.
1 = program counter bank register is pushed onto the stack, pc is incremented by 2 and pushed on stack, status register pushed on stack, irq disable flag set, program bank register is cleared to 0, pc is loaded from $00ffe4, $00ffe5.
i1 – interrupts are disabled when the ISR is called.
m
n
v
x
z
Flags affecting operation.

AddressingSyntaxProcessorOpCodeCycles Bytes
stack/interruptCOP const65c816$B87
+1 if e=0.
1
+1 for optional identifier byte.
Valid addressing modes.

CPX

Compare memory and index X.

Compares the data referenced by the parameter to the contents of the X register. This is an internal subtraction operation where the data is subtracted from the X register and the processor flags are set accordingly. The result of the subtraction is discarded, neither the referenced data nor the X register are changed. Note also that the value of the carry flag is not used in the operation and the overflow flag is not set, this means CPX only good for unsigned comparisons.

FlagEffect on ExecutionValue after Execution
b
c1 = no borrow required (x register >= data).
0 = borrow required (x register < data).
d
i
m
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x0 = comparison is 16 bits on 65816.
1 = comparison is 8 bits on 65816.
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteCPX addr65c02$EC4
+1 if x=0.
3
direct page (dp)CPX dp65c02$E43
+1 if x = 0.
+1 if low byte of dp register <> 0.
2
immediateCPX #const65c02$E02
+1 if x = 0.
2
+1 if x = 0.
Valid addressing modes.

CPY

Compare memory and index Y.

Compares the data referenced by the parameter to the contents of the Y register. This is an internal subtraction operation where the data is subtracted from the Y register and the processor flags are set accordingly. The result of the subtraction is discarded, neither the referenced data nor the Y register are changed. Note also that the value of the carry flag is not used in the operation and the overflow flag is not set, this means CPY only good for unsigned comparisons.

FlagEffect on ExecutionValue after Execution
b
c1 = no borrow required (y register >= data).
0 = borrow required (y register < data).
d
i
m
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x0 = comparison is 16 bits on 65816.
1 = comparison is 8 bits on 65816.
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteCPY addr65c02$CC4
+1 if x=0.
3
direct page (dp)CPY dp65c02$C43
+1 if x = 0.
+1 if low byte of dp register <> 0.
2
immediateCPY #const65c02$C02
+1 if x = 0.
2
+1 if x = 0.
Valid addressing modes.

DEC

Decrement memory or accumulator by one.

Decrements the contents of the location specified by the operand, or the accumulator. DEC is not affected by the carry flag, nor does it set it. DEC does set the zero and negative flags. DEC is not affected by the d flag.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m0 = Data decremented is 16 bits.
1 and 65c02 = Data decremented is 8 bits.
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
accumulatorDEC A65c02$3A21
absoluteDEC addr65c02$CE6
+2 if m = 0.
1
absolute indexed, xDEC addr, X65c02$DE7
+1 if m = 0.
-1 if 65c02 and no page boundary crossed.
3
direct page (dp)DEC dp65c02$C65
+2 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indexed, xDEC dp, X65c02$D66
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
Valid addressing modes.

DEX

Decrement index X by one.

Decrement the contents of the index register X by one. DEX does not affect the carry flag, nor is it affected by it. DEX does set the n and z flags.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x0 = Data decremented is 16 bits.
1 and 65c02 = Data decremented is 8 bits.
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedDEX65c02$CA21
Valid addressing modes.

DEY

Decrement index Y by one.

Decrement the contents of the index register Y by one. DEY does not affect the carry flag, nor is it affected by it. DEY does set the n and z flags.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x0 = Data decremented is 16 bits.
1 and 65c02 = Data decremented is 8 bits.
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedDEY65c02$8821
Valid addressing modes.

EOR

“Exclusive OR” memory with accumulator.

Bitwise logical “Exclusive OR” the data specified with the contents of the accumulator, placing the result in the accumulator.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m0 = Data is 16 bits.
1 and 65c02 = Data is 8 bits.
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteEOR addr65c02$4D4
+1 if m = 0.
3
absolute indexed, xEOR addr, X65c02$5D4
+1 if m = 0.
+1 if adding index crosses page boundary.
3
absolute indexed, yEOR addr, Y65c02$594
+1 if m = 0.
+1 if adding index crosses page boundary.
3
absolute longEOR long65c816$4F5
+1 if m = 0.
4
absolute long indexed, xEOR long, X65c816$5F5
+1 if m = 0.
4
direct page (dp)EOR dp65c02$453
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indexed, xEOR dp, X65c02$554
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indexed indirect, xEOR (dp, X)65c02$416
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indirectEOR (dp)65c02$525
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indirect indexed, yEOR [dp], Y65c816$576
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indirect longEOR [dp]65c816$476
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
immediateEOR #const65c02$492
+1 if m = 0.
2
+1 if m = 0.
stack relative (sr)EOR sr, S65c816$437
+1 if m = 0.
2
sr indirect indexed, yEOR (sr, S), Y65c816$537
+1 if m = 0.
2
Valid addressing modes.

INC

Increment memory or accumulator by one.

Increments the contents of the location specified by the operand, or the accumulator. INC is not affected by the carry flag, nor does it set it. INC does set the zero and negative flags. INC is not affected by the d flag.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m0 = Data incremented is 16 bits.
1 and 65c02 = Data incremented is 8 bits.
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
accumulatorINC A65c02$1A21
absoluteINC addr65c02$EE6
+2 if m = 0.
1
absolute indexed, xINC addr, X65c02$FE7
+1 if m = 0.
-1 if 65c02 and no page boundary crossed.
3
direct page (dp)INC dp65c02$E65
+2 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indexed, xINC dp, X65c02$F66
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
Valid addressing modes.

INX

Increment index X by one.

Increment the contents of the index register X by one. INX does not affect the carry flag, nor is it affected by it. INX does set the n and z flags.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x0 = Data incremented is 16 bits.
1 and 65c02 = Data incremented is 8 bits.
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedINX65c02$E821
Valid addressing modes.

INY

Increment index Y by one.

Increment the contents of the index register Y by one. INY does not affect the carry flag, nor is it affected by it. INY does set the n and z flags.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n1 = most significant bit of result is set.
0 = most significant bit of result is not set.
v
x0 = Data incremented is 16 bits.
1 and 65c02 = Data incremented is 8 bits.
z1 = result is zero.
0 = result is non-zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedINY65c02$C821
Valid addressing modes.

JML*

Jump long.

The program counter and program counter bank are loaded with the address given in the operand and execution resumes from there.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absolute indirect longJML [addr]65c816$DC63
absolute longJML long65c816$5C44
Valid addressing modes.

JMP

Jump to new location.

The program counter is loaded with the address given in the operand and execution resumes from there.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteJMP addr65c02$4C33
absolute indexed indirectJMP (addr, X)65c02$7C63
absolute indirectJMP (addr)65c02$6C5
+1 if 65c02
3
absolute indirect longJMP [addr]
or
JML [addr]
65c816$DC63
absolute longJMP long
or
JML long
65c816$5C44
Valid addressing modes.

JSL*

Jump subroutine long.

Transfers control to the subroutine specified by the 24-bit operand. The current 24-bit return address is pushed onto the stack before the jump is executed. The return address is the address of the last byte of this instruction (so, the actual return address -1). The current program counter bank is pushed first, then the high byte and then low byte of the return address.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absolute longJSL long
or
JSR long
65c816$5C84
Valid addressing modes.

JSR

Jump to new location, saving return.

Transfers control to the subroutine specified by the operand. The current return address is pushed onto the stack before the jump is executed. The return address is the address of the last byte of this instruction (so, the actual return address -1). The current program counter bank is pushed first if a long address is used (address > $FFFF), then the high byte and then low byte of the return address.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteJSR addr65c02$2063
absolute indexed indirectJSR (addr, X)65c02$FC83
absolute longJSR long
or
JSL long
65c816$2284
Valid addressing modes.

LDA

Load accumulator with memory.

Loads the data located at the specified address into the accumulator.

FlagEffect on ExecutionValue after Execution
b
c
d
i
mm = 0 on 65c816, then data is 16-bit.
nmost significant bit of data.
v
x
z1 = data = 0.
0 = data <> 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteLDA addr65c02$AD4
+1 if m = 0.
3
absolute indexed, xLDA addr, X65c02$BF4
+1 if m = 0.
+1 if adding index crosses page boundary.
3
absolute indexed, yLDA addr, Y65c02$B94
+1 if m = 0.
+1 if adding index crosses page boundary.
3
absolute longLDA long65c816$AF5
+1 if m = 0.
4
absolute long indexed, xLDA long, X65c816$BF5
+1 if m = 0.
4
direct page (dp)LDA dp65c02$A53
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indexed, xLDA dp, X65c02$B54
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indexed indirect, xLDA (dp, X)65c02$A16
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indirectLDA (dp)65c02$B25
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indirect indexed, yLDA (dp), Y65c816$B16
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indirect longLDA [dp]65c816$A76
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indirect long indexed, yLDA [dp], Y65c816$B76
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
immediateLDA #const65c02$A92
+1 if m = 0.
2
+1 if m = 0.
stack relative (sr)LDA sr, S65c816$A37
+1 if m = 0.
2
sr indirect indexed, yLDA (sr, S), Y65c816$B37
+1 if m = 0.
2
Valid addressing modes.

LDX

Load index x with memory.

Loads the data located at the specified address into the X index register.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
nmost significant bit of data.
v
xx = 0 on 65c816, then data is 16-bit.
z1 = data = 0.
0 = data <> 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteLDX addr65c02$AE4
+1 if x = 0.
3
absolute indexed, yLDX addr, Y65c02$BE4
+1 if x = 0.
+1 if adding index crosses page boundary.
3
direct page (dp)LDX dp65c02$A63
+1 if x = 0.
+1 if low byte of dp register <> 0.
2
dp indexed, yLDX dp, Y65c816$B64
+1 if x = 0.
+1 if low byte of dp register <> 0.
2
immediateLDX #const65c02$A22
+1 if x = 0.
2
+1 if x = 0.
Valid addressing modes.

LDY

Load index y with memory.

Loads the data located at the specified address into the Y index register.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
nmost significant bit of data.
v
xx = 0 on 65c816, then data is 16-bit.
z1 = data = 0.
0 = data <> 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteLDY addr65c02$AC4
+1 if x = 0.
3
absolute indexed, xLDY addr, X65c02$BC4
+1 if x = 0.
+1 if adding index crosses page boundary.
3
direct page (dp)LDY dp65c02$A43
+1 if x = 0.
+1 if low byte of dp register <> 0.
2
dp indexed, xLDY dp, X65c02$B44
+1 if x = 0.
+1 if low byte of dp register <> 0.
2
immediateLDY #const65c02$A02
+1 if x = 0.
2
+1 if x = 0.
Valid addressing modes.

LSR

Shift accumulator or memory one bit right.

This is the arithmetic equivalent of unsigned division by 2. The bits in the location specified by the operand are shifted one bit to the right. The lowest-significant bit is shifted into the carry flag. 0 is shifted into the most-significant bit.

FlagEffect on ExecutionValue after Execution
b
c
d
i
mm = 0 on 65c816, then data is 16-bit.
n
v
x
z1 = data = 0.
0 = data <> 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteLSR addr65c02$4E6
+1 if m = 0.
3
absolute indexed, xLSR addr, X65c02$5E7
+1 if m = 0.
-1 if 65c02 and no page boundary crossed.
3
accumulatorLSR A65c02$4A21
direct page (dp)LSR dp65c02$465
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indexed, xLSR dp, X65c02$566
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
Valid addressing modes.

MVN*

Block move next.

Copies a block of memory from a source address to a target address. This differs from MVP in that the source and target addresses are interpreted by MVN as the start of the memory block. Bytes are copied from incrementing source addresses to incrementing target addresses until the specified number of bytes + 1 have been copied. The source address is put in index X, the target address is put in index Y and the number of bytes to copy – 1 is put in the accumulator. The operands to the instruction are the source bank and destination bank.

If the source and target areas overlap, this instruction should only be used if the target address is lower than the source address. If the target is higher than the source address, then use MVP.

In 6502 emulation mode, the bank operands should always be 0.

If a block move is interrupted, it may be resumed automatically upon an RTI instruction if all registers are restored or intact. The current byte copy is completed before an interrupt is serviced.

For example:

; source = $0000
; target = $0200
; bytes to copy = 3
ldx #$0000
ldy #$0200
lda #$0002 ; bytes to copy - 1
mvn #$00, #$00

would be equivalent to:

; incrementing addresses
lda $0000
sta $0200
lda $0001
sta $0201
lda $0002
sta $0202

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
block moveMVN srcbk, destbk65c816$547 cycles per byte copied.3
Valid addressing modes.

MVP*

Block move previous.

Copies a block of memory from a source address to a target address. This differs from MVN in that the source and target addresses are interpreted by MVP as the end of the memory block. Bytes are copied from decrementing source addresses to decrementing target addresses until the specified number of bytes + 1 have been copied. The source address is put in index X, the target address is put in index Y and the number of bytes to copy – 1 is put in the accumulator. The operands to the instruction are the source bank and destination bank.

If the source and target areas overlap, this instruction should only be used if the target address is higher than the source address. If the target is lower than the source address, then use MVN.

In 6502 emulation mode, the bank operands should always be 0.

If a block move is interrupted, it may be resumed automatically upon an RTI instruction if all registers are restored or intact. The current byte copy is completed before an interrupt is serviced.

For example:

; source = $0000
; target = $0200
; bytes to copy = 3
ldx #$0200
ldy #$0000
lda #$0002 ; bytes to copy - 1
mvn #$00, #$00

would be equivalent to:

; decrementing addresses
lda $0202
sta $0002
lda $0201
sta $0001
lda $0200
sta $0000

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
block moveMVP srcbk, destbk65c816$447 cycles per byte copied.3
Valid addressing modes.

NOP

No operation.

Takes no action other than to advance the program counter. No flags or memory are affected.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedNOP65c02$EA21
Valid addressing modes.

ORA

“OR” memory with accumulator.

Performs a bitwise logical “OR” of the data located at the effective address specified by the operand with the contents of the accumulator, placing the result in the accumulator.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m0 = 16 bit data/accumulator.
1 and 65c02 = 8 bit data/accumulator.
n1 = most significant bit of result.
v
x
z0 = result is non-zero.
1 = result is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteORA addr65c02$0D4
+1 if m=0
+1 if 65c02 and d=1
3
absolute indexed, xORA addr, X65c02$1D4
+1 if page crossed
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
3
absolute indexed, yORA addr, Y65c02$194
+1 if page crossed
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
3
absolute longORA long65c816$0F5
+1 if m=0
4
absolute long indexed, xORA long, X65c816$1F5
+1 if m=0
4
direct page (dp)ORA dp65c02$053
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
stack relativeORA sr, S65c816$034
+1 if m=0
2
dp indexed, xORA dp, X65c02$154
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
dp indirectORA (dp)65c02$125
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
dp indirect longORA [dp]65c816$076
+1 if m=0
+1 if low byte of dp register is nonzero
2
sr indirect indexed, yORA (sr, S), Y65c816$137
+1 if m=0
2
dp indexed indirect, xORA (dp, X)65c02$016
+1 if m=0
+1 if 65c02 and d=1
+1 if low byte of dp register is nonzero
2
dp indirect indexed, yORA (dp, Y)65c02$115
+1 if page crossed
+1 if m=0
+1 if 65c02 and d=1
+1 if adding index crosses page boundary
+1 if low byte of dp register is nonzero
2
dp indirect long indexed, yORA [dp], Y65c816$176
+1 if m=0
+1 if low byte of dp register is nonzero
2
immediateORA #const65c02$092
+1 if m=0
+1 if 65c02 and d=1
2
+1 if m=0
Valid addressing modes.

PEA*

Push absolute address.

Pushes the 16-bit operand onto the stack. The stack pointer is decremented twice and this instruction always pushes 16 bits of data, regardless of the m and x flag settings. Note that this instruction pushes the actual operand onto the stack, not the data stored at the address denoted by the operand.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (absolute)PEA addr65c816$F435
Valid addressing modes.

PEI*

Push indirect address.

Pushes the 16-bit value located at the address formed by adding the direct page offset specified by the operand to the direct page register. The data doesn’t necessarily have to be an address. This instruction always pushes 16 bits of data, regardless of the setting of the m and x flags. The effective indirect address, rather than the data stored at the address is what is pushed onto the stack.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (direct page indirect)PEI (dp)65c816$D46
+1 if low byte of dp register <> 0
2
Valid addressing modes.

PER*

Push program counter relative address.

Adds the current value of the program counter to the 16-bit unsigned displacement in the operand and pushes the result onto the stack. This instruction always pushes 16 bits, regardless of the settings of the m and x flags.

This instruction is helpful in writing relocatable code, in which an address within the program must be accessed. The address pushed onto the stack will be the runtime address of the data area, regardless of where the program was loaded in memory. It may be pulled into a register, stored in an indirect pointer or used on the stack with the stack relative indirect indexed addressing mode to access the data at that location.

The syntax used is to specify as the operand the label of the data area you want to reference. This location must be in the program bank, since the displacement is relative to the program counter. The assembler converts the assembly-time label into a displacement from the assembly-time address of the next instruction.

The value of the program counter used in the addition is the address of the next instruction (the instruction following the PER instruction).

PER can also be used to push return addresses onto the stack, either as part of a simulated branch-to-subroutine or to place the return address beneath the stacked parameters to a subroutine call. Not that a pushed return address should be the desired return address minus one.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (program counter relative long)PER label6c816$6236
Valid addressing modes.

PHA

Push accumulator on stack.

Pushes the accumulator onto the stack.

$01ff (s register, top of stack) ->xx
Stack before PHA (8 and 16 bit)
$01ff8 bit accumulator contents
$01fe (s register, after pha) ->xx
Stack after PHA (8 bit)
$01ffupper 8 bits of accumulator contents
$01felower 8 bits of accumulator contents
$01fd (s register, after pha) ->xx
Stack after PHA (16 bit)
FlagEffect on ExecutionValue after Execution
b
c
d
i
m0 = data pushed is 16 bits.
1 or on 65c02 = data pushed is 8 bits.
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (push)PHA65c02$483
+1 if m = 0
1
Valid addressing modes.

PHB*

Push data bank register on stack.

Pushes the contents of the data bank register onto the stack. This is only one byte, no matter the value of the m and x flags.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (push)PBH65c816$8B31
Valid addressing modes.

PHD*

Push direct register on stack.

Pushes the contents of the direct page register onto the stack. This is always a 16-bit operation, regardless of the setting of the m and x flag.

By pushing the D register onto the stack, the local environment of a calling subroutine may easily be saved by a called subroutine before modifying the D register to provide islets with its own direct page memory.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (push)PHB65c816$0B41
Valid addressing modes.

PHK*

Push program bank register on stack.

Pushes the program bank register onto the stack. This is always an 8-bit value, regardless of the setting of m and x.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (push)PHK65c816$4B31
Valid addressing modes.

PHP

Push processor status on stack.

Push the contents of the processor status register onto the stack. This is always an 8-bit value, regardless of the setting of the m and x flags. This does not preserve the e flag. The only way to access the e flag is via the XCE instruction.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (push)PHP65c02$0831
Valid addressing modes.

PHX

Push index x on stack.

$01ff (s register, top of stack) ->xx
Stack before PHX (8 and 16 bit)
$01ff8 bit register x contents
$01fe (s register, after phi) ->xx
Stack after PHX (8 bit)
$01ffupper 8 bits of register x contents
$01felower 8 bits of register x contents
$01fd (s register, after phx) ->xx
Stack after PHX (16 bit)
FlagEffect on ExecutionValue after Execution
b
c
d
i
m0 = data pushed is 16 bits.
1 or on 65c02 = data pushed is 8 bits.
n
v
x
z
Flags affecting operation.

Pushes the contents of the X index register onto the stack. This will either push 8 bits or 16 bits of data, depending on the x flag.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x0 = 16 bits of data pushed.
1 and on 65c02 = 8 bits pushed.
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (push)PHX65c02$DA3
+1 if x = 0.
1
Valid addressing modes.

PHY

Push index y on stack.

Pushes the contents of the Y index register onto the stack. This will either push 8 bits or 16 bits of data, depending on the x flag.

$01ff (s register, top of stack) ->xx
Stack before PHY (8 and 16 bit)
$01ff8 bit register y contents
$01fe (s register, after phy) ->xx
Stack after PHY (8 bit)
$01ffupper 8 bits of register y contents
$01felower 8 bits of register y contents
$01fd (s register, after phy) ->xx
Stack after PHY (16 bit)
FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x0 = 16 bits of data pushed.
1 and on 65c02 = 8 bits pushed.
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (push)PHY65c02$5a3
+1 if x = 0
1
Valid addressing modes.

PLA

Pull accumulator from stack.

Pulls the value in the top of the stack into the accumulator.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m0 = 16 bits are pulled.
1 and on 65c02 = 8 bits are pulled.
nset to the most significant bit of the pulled data.
v
x
z0 = value pulled is nonzero
1 = value pulled is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (pull)PLA65c02$684
+1 if m = 0
1
Valid addressing modes.

PLB*

Pull data bank register from stack.

Pulls the 8-bit value on top of the stack into the data bank register B, switching the data bank to that value. This is the only instruction that can modify the data bank register. Since the data bank register is only 8 bits, this instruction always pulls 8 bits from the stack, regardless of the setting of the m and x flags.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
nset to the most significant bit of the data bank register.
v
x
z0 = value pulled is nonzero.
1 = value pulled is 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (pull)PLB65c816$AB41
Valid addressing modes.

PLD*

Pull direct register from stack.

Pull the 16 bit value on top of the stack into the direct page register D, switching the direct page to that value. PLD is typically used to restore the direct page register to a previous value.

Since the direct page register is a 16-bit register, two bytes are always pulled from the stack, regardless of the value of the m and x flags.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
nmost significant bit of the pulled value.
v
x
z0 = pulled value is nonzero.
1 = pulled value is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (pull)PLD65c816$2B51
Valid addressing modes.

PLP

Pull processor status from stack.

Pulls the 8-bit value on the top of the stack into the processors status register P, switching the status byte to that value.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (pull)PLP65c02$2841
Valid addressing modes.

PLX

Pull index x from stack.

Pulls the value on the top of the stack into the X index register.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
nset to the most significant bit of the data.
v
x0 = 16 bits are pulled.
1 and always on 65c02 = 8 bits are pulled.
z0 = pulled data is nonzero.
1 = pulled data is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (pull)PLX65c02$FA4
+1 if x = 0.
1
Valid addressing modes.

PLY

Pull index y from stack.

Pulls the value on the top of the stack into the Y index register.

FlagEffect on ExecutionValue after Execution
b
c
d
i
m
nset to the most significant bit of the data.
v
x0 = 16 bits are pulled.
1 and always on 65c02 = 8 bits are pulled.
0 = pulled data is nonzero.
1 = pulled data is zero.
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (pull)PLY65c02$7A4
+1 if x = 0.
1
Valid addressing modes.

REP*

Reset flag bits.

This instruction takes a bit mask as an operand. Each bit that is set in the operand will cause the corresponding bit in the status register to reset to 0. If a bit in the mask operand is 0, the corresponding bit in the status register remains unchanged.

76543210
nvmxdizc
negativeoverflow8 bit memory/accumulator8 bit index registersdecimalirq interrupt disablezero resultcarry
65c816 Flags
FlagEffect on ExecutionValue after Execution
c0 = bit 0 is set in the REP operand. otherwise, unchanged
d0 = bit 3 is set in the REP operand. otherwise, unchanged.
e0 = all flags are modifiable.
1 = the break flag and bit 5 are unaffected by REP.
i0 = bit 2 is set in the REP operand. otherwise, unchanged.
m0 = bit 5 is set in the REP operand. otherwise, unchanged.
n0 = bit 7 is set in the REP operand. otherwise, unchanged.
v0 = bit 6 is set in the REP operand. otherwise, unchanged.
x0 = bit 4 is set in the REP operand. otherwise, unchanged.
z0 = bit 1 is set in the REP operand. otherwise, unchanged.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
immediateREP #const65c816$C232
Valid addressing modes.

ROL

Rotate accumulator or memory one bit left.

Rotate the contents of the location specified by the operand left one bit. Bit 0 will take the value in the carry flag and the carry flag will receive the value of the most significant bit.

FlagEffect on ExecutionValue after Execution
b
cthe original most significant bit
d
i
m0 = 16 bits of data are rotated.
1 and 65c02 = 8 bits are rotated.
nmost significant bit of result.
v
x
z0 = result is non-zero.
1 = result is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteROL addr65c02$2E6
+2 if m = 0.
3
absolute indexed, xROL addr, X65c02$3E7
+2 if m = 0.
-1 if 65c02 and no page boundary crossed.
3
accumulatorROL65c02$2A21
direct page (dp)ROL dp65c02$265
+2 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indexed, xROL dp, X65c02$366
+2 if m = 0.
+1 if low byte of dp register <> 0.
2
Valid addressing modes.

ROR

Rotate accumulator or memory one bit right.

Rotate the contents of the location specified by the operand right one bit. The most significant bit will take the value in the carry flag and the carry flag will receive the value of the least significant bit (bit 0).

FlagEffect on ExecutionValue after Execution
b
cleast significant bit of original value
d
i
m0 = 16 bits of data are rotated.
1 and 65c02 = 8 bits of data are rotated.
nmost significant bit of result.
v
x
z0 = result is non-zero.
1 = result is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteROR addr65c02$6E6
+2 if m = 0.
3
absolute indexed, xROR addr, X65c02$7E7
+2 if m = 0.
-1 if 65c02 and no page boundary crossed.
3
accumulatorROR65c02$6A21
direct page (dp)ROR dp65c02$665
+2 if m = 0.
+1 if low byte of dp register <> 0.
2
dp indexed, xROR dp, X65c02$766
+2 if m = 0.
+1 if low byte of dp register <> 0.
2
Valid addressing modes.

RTI

Return from interrupt

Pulls the status register and the program counter from the stack. On the 65c816 in native mode, also pulls the program bank register from the stack. Unlike the RTS instruction, the program counter address pulled off the stack is the exact address to return to. Pulling the status register gives the status flags the values they had immediately prior to the start of interrupt processing.

STACK
stack pointer after RTI->Old Status Register
Return Address Bank
Return Address High
Return Address Low
stack pointer before RTI->
BANK 0
Native Mode Stack before and after RTI.
FlagEffect on ExecutionValue after Execution
b
cRestored to value prior to interrupt.
dRestored to value prior to interrupt.
iRestored to value prior to interrupt.
mRestored to value prior to interrupt (65c816).
nRestored to value prior to interrupt.
vRestored to value prior to interrupt.
xRestored to value prior to interrupt (65c816).
zRestored to value prior to interrupt.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (rti)RTI65c02$406
+1 on 65816 in native mode.
1
Valid addressing modes.

RTL*

Return from subroutine long.

Pulls the program counter (incrementing the stacked, 16-bit value by one before loading the program counter with it), then the program bank register from the stack.

When a subroutine in another bank is called (via a jump to subroutine long instruction), the current bank address is pushed onto the stack along with the return address. To return to the calling bank, a long return instruction must be executed, which first pulls the return address from the stack and loads the program bank register. This transfer control to the instruction immediately following the original jump to subroutine long.

STACK
stack pointer after RTI->Return Address Bank
Return Address High
Return Address Low
stack pointer before RTI->
BANK 0
Native Mode Stack before and after RTI.
FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (rtl)RTL65c816$6B61
Valid addressing modes.

RTS

Return from subroutine.

Pulls the program counter, incrementing the stacked, 16-bit value by one before loading the program counter with it.

When a subroutine is called (via a jump to subroutine instruction), the current address is pushed onto the stack. To return to the code following the subroutine call, a return instruction must be executed, which pulls the return address from the stack, increments it and loads the program counter with it, transferring control to the instruction immediately following the jump to subroutine.

STACK
stack pointer after RTS->Return Address High
Return Address Low
stack pointer before RTS->
BANK 0
Stack before and after RTS.
FlagEffect on ExecutionValue after Execution
b
c
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
stack (rts)RTS65c02$6061
Valid addressing modes.

SBC

Subtract memory from accumulator.

Subtracts the data located at the effective address specified by the operand from the contents of the accumulator. If the carry flag is clear, an additional 1 will be subtracted. The result is stored in the accumulator.

The 65x family of processors do not have a subtract instruction which does not use the carry flag. To avoid using the carry, make sure that it is set before the SBC instruction is executed. It can be explicitly set with SEC.

In a multi-word subtract, set the carry before the low words are subtracted. The low word subtraction then generates a new carry value for the subtraction of the next highest word, etc.

FlagEffect on ExecutionValue after Execution
b
c0 = unsigned borrow required.
1 = unsigned borrow not required.
d0 = binary subtraction.
1 = BCD subtraction.
i
m0 = data subtracted is 16 bits.
1 and on 65c02 = data subtracted is 8 bits.
nset to the most significant bit of the result.
v0 = valid signed result.
1 = signed overflow.
x
z0 = result is non-zero.
1 = result is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteSBC address65c02$ED4
+1 if m=0.
3
absolute indexed, xSBC address, X65c02$FD4
+1 if m=0.
+1 if adding index crosses page boundary.
3
absolute indexed, ySBC address, Y65c02$F94
+1 if m=0.
+1 if if adding index crosses page boundary.
3
absolute longSBC long65c816$EF5
+1 if m=0.
4
absolute long indexed, xSBC long, X65c816$FF5
+1 if m=0.
4
direct page (dp)SBC dp65c02$E53
+1 if m=0.
+1 if low byte of dp register <> 0.
2
dp indexed, xSBC dp, X65c02$F56
+1 if m=0.
+1 if low byte of dp register <> 0.
2
dp indexed indirect, xSBC (dp, X)65c02$E16
+1 if m=0.
+! if low order byte of dp register <> 0.
2
dp indirect indexed, ySBC (dp), Y65c02$F15
+1 if m=0.
+1 if low byte of dp register <> 0.
+1 if adding index crosses page boundary.
2
dp indirectSBC (dp)65c02$F25
+1 if m=0.
+1 if low byte of dp register <> 0.
2
dp indirect longSBC [dp]65c816$E76
+1 if m=0.
+1 if low byte of dp register <> 0.
2
dp indirect long indexed, ySBC [dp], Y65c816$F76
+1 if m=0.
+1 if low byte of dp register <> 0.
2
immediateSBC #const65c02$E92
+1 if m=0.
2
+1 if m=0.
sr indirect indexed, ySBC (sr, S), Y65c816$F37
+1 if m=0.
2
stack relative (sr)SBC sr, S65c816$E37
+1 if m=0.
2
Valid addressing modes.

SEC

Set carry flag.

Sets the carry flag in the status register. SEC can be used prior to subtraction to keep the carry flag from affecting the result. It is also used prior to the XCE instruction to put the 65c816 into 6502 emulation mode.

FlagEffect on ExecutionValue after Execution
b
csets the carry flag to 1.
d
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedSEC65c02$3821
Valid addressing modes.

SED

Set decimal mode.

Set the decimal mode flag in the status register. This puts the processor into decimal mode from binary mode, so that the ADC and SBC instructions will operate correctly on BCD data and automatically perform decimal adjustment.

FlagEffect on ExecutionValue after Execution
b
c
dset to 1.
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedSED65c02$F821
Valid addressing modes.

SEI

Set interrupt disable status.

Set the interrupt disable flag in the status register. When the i bit is set, maskable hardware interrupts are ignored. The processor itself will set the i flag when it begins servicing an interrupt request. Thus, interrupt handling code should reenable interrupts with CLI if they are interruptible. If interrupts are to remain blocked during the execution of the interrupt handling code, exiting the routine via RTI will automatically restore the status register with the i flag clear, re-enabling interrupts.

FlagEffect on ExecutionValue after Execution
b
c
d
iset to 1.
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedSEI65c02$7821
Valid addressing modes.

SEP*

Set flag bits.

This instruction takes a bit mask as an operand. Each bit that is set in the operand will cause the corresponding bit in the status register to set to 1. If a bit in the mask operand is 0, the corresponding bit in the status register remains unchanged.

76543210
nvmxdizc
negativeoverflow8 bit memory/accumulator8 bit index registersdecimalirq interrupt disablezero resultcarry
65c816 Flags
FlagEffect on ExecutionValue after Execution
c1 = bit 0 is set in the SEP operand. otherwise, unchanged
d1 = bit 3 is set in the SEP operand. otherwise, unchanged.
e0 = all flags are modifiable.
1 = the break flag and bit 5 are unaffected by SEP.
i1 = bit 2 is set in the SEP operand. otherwise, unchanged.
m1 = bit 5 is set in the SEP operand. otherwise, unchanged.
n1 = bit 7 is set in the SEP operand. otherwise, unchanged.
v1 = bit 6 is set in the SEP operand. otherwise, unchanged.
x1 = bit 4 is set in the SEP operand. otherwise, unchanged.
z1 = bit 1 is set in the SEP operand. otherwise, unchanged.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
immediateSEP #const65c816$E232
Valid addressing modes.

STA

Store accumulator in memory.

Store the value in the accumulator to the effective address specified by the operand.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m0 = data is 16 bits.
1 and on 65c02 = data is 8 bits.
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteSTA addr65c02$8D4
+1 if m = 0.
3
absolute indexed, xSTA addr, X65c02$9D5
+1 if m = 0.
3
absolute indexed, ySTA addr, Y65c02$995
+1 if m = 0.
3
absolute longSTA long65c816$8F5
+1 if m = 0.
4
absolute long indexed, xSTA long, X65c816$9F5
+1 if m = 0.
4
direct page (dp)STA dp65c02$853
+1 if m = 0.
+1 if low byte of direct page register <> 0.
2
dp indexed, xSTA dp, X65c02$954
+1 if m = 0.
+1 if low byte of direct page register <> 0.
2
dp indexed indirect, xSTA (dp, X)65c02$816
+1 if m = 0.
+1 if low byte of direct page register <> 0.
2
dp indirectSTA (dp)65c02$925
+1 if m = 0.
+1 if low byte of direct page register <> 0.
2
dp indirect indexed, ySTA (dp), Y65c02$916
+1 if m = 0.
+1 if low byte of direct page register <> 0.
2
dp indirect longSTA [dp]65c816$876
+1 if m = 0.
+1 if low byte of direct page register <> 0.
2
dp indirect long indexed, ySTA [dp], Y65c816$976
+1 if m = 0.
+1 if low byte of direct page register <> 0.
2
stack relative (sr)STA sr, s65c816$834
+1 if m = 0.
2
stack indirect indexed, ySTA (sr, S), Y65c816$937
+1 if m = 0.
2
Valid addressing modes.

STP

Stop the processor.

During the processor’s next phase 2 clock cycle, stops the processor’s oscillator input. The processor is effectively shut down until a reset occurs (/RES pin is pulled low).

This is designed to put the processor to sleep while it’s not actively in use, in order to reduce power consumption.

The reset handling routine ($00:FFFC-$00:FFFD) should be designed to either reinitialize the system or resume control though a previously-installed reset handler.

Reset is an interrupt-like signal that causes the emulation bit to be set to one. It also causes the direct page register to reset to 0, stack high to set to one (forcing the stack page pointer to page one) and the mode select flags to be set to one (8-bit registers, so the high bytes of the index registers are zeroed).

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedSTP65c816$DB3
3 cycles to shut the processor down. additional cycles are required by reset to restart it.
1
Valid addressing modes.

STX

Store index X in memory.

Store the value in the index register X to the effective address specified by the operand.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
n
v
x0 = data is 16 bits.
1 and on 65c02 = data is 8 bits.
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteSTX addr65c02$8E4
+1 if x = 0.
3
direct pageSTX dp65c02$863
+1 if x = 0.
+1 if low byre of direct page register <> 0.
2
direct page indexed, ySTX dp, Y65c02$964
+1 if x = 0.
+1 if low byte of direct page register <> 0.
2
Valid addressing modes.

STY

Store index Y in memory.

Store the value in the index register Y to the effective address specified by the operand.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
n
v
x0 = data is 16 bits.
1 and on 65c02 = data is 8 bits.
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteSTX addr65c02$8C4
+1 if x = 0.
3
direct pageSTX dp65c02$843
+1 if x = 0.
+1 if low byre of direct page register <> 0.
2
direct page indexed, xSTX dp, X65c02$944
+1 if x = 0.
+1 if low byte of direct page register <> 0.
2
Valid addressing modes.

STZ

Store zero in memory.

Stores 0 to the effective address specified by the operand.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m0 = data is 16 bits.
1 and on 65c02 = data is 8 bits.
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteSTZ addr65c02$9C4
+1 if m = 0.
3
absolute indexed, xSTZ addr, X65c02$9E5
+1 if m = 0.
3
direct pageSTZ dp65c02$643
+1 if m = 0.
+1 if low byre of direct page register <> 0.
2
direct page indexed, xSTZ dp, X65c02$744
+1 if m = 0.
+1 if low byte of direct page register <> 0.
2
Valid addressing modes.

SWA*

Swap the high and low bytes of the 16-bit A accumulator.

B represents the high-order byte of the 16 bit C accumulator, and A in this case represents the low-order byte. XBA swaps the contents of the low-order and high-order bytes of C.

An alternate mnemonic is XBA (Exchange the B and A accumulators).

SWA can be used to invert the low-order, high-order arrangement of a 16-bit value, or to temporarily store an 8-bit value from the A accumulator into B. Since it is an exchange, the previous contents of both accumulators are changed, replaced by the previous contents of the other.

Neither mode select flags nor the emulation mode flag affects this operation.

The flags are changed based on the new value of the low byte the A accumulator (that is, on the former value of the high byte, the B accumulator), even in 16 bit accumulator mode.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nset to the most significant bit of the value that is transferred from the B accumulator to the A accumulator.
v
x
z0 = 8 bit value transferred to A accumulator is non-zero.
1 = 8 bit value transferred to A accumulator is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedSWA (or XBA)65c816$EB31
Valid addressing modes.

TAD*

Transfer A accumulator to Direct Register.

Transfers the value in the 16-bit accumulator (A) to the Direct Page register D, regardless of the setting of the accumulator/memory mode flag.

An Alternate mnemonic is TCD (Transfer C accumulator to Direct Page register).

If the A accumulator is set to just eight bits (whether because of the m flag or because the processor is in 6502 emulation mode), then its value becomes the low byte of the Direct Page register and the value in the hidden B accumulator becomes the high byte of the Direct Page register.

The accumulator’s 16 bit value is unchanged by the operation.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nSet to the most significant bit of the transferred value.
v
x
z0 = transferred value <> 0.
1 = transferred value == 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTAD (or TCD)65c816$5B21
Valid addressing modes.

TAS*

Transfer A accumulator to Stack Pointer register.

Transfers the value of the accumulator to the Stack Pointer S. The accumulator’s value is unchanged.

An alternate mnemonic is TCS (Transfer C accumulator to Stack Pointer register).

If the A accumulator is set to just eight bits (whether because of the m flag or because the processor is in 6502 emulation mode), then its value becomes the low byte of the Stack Pointer register and the value in the hidden B accumulator becomes the high byte of the Stack Pointer register.

The accumulator’s 16 bit value is unchanged by the operation.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nSet to the most significant bit of the transferred value.
v
x
z0 = transferred value <> 0.
1 = transferred value == 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTAS (or TCS)65c816$1B21
Valid addressing modes.

TAX

Transfer accumulator to index X.

Transfers the value in the accumulator to the index register X. If the registers are different sizes, the nature of the transfer is determined by the X register. TAX does not change the value in the accumulator.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nmost significant bit of the value transferred.
v
x0 = value transferred is 16 bits.
1 = the lower 8 bits of the accumulator are transferred.
z0 = result in x <> 0.
1 = result in x == 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTAX65c02$AA21
Valid addressing modes.

TAY

Transfer accumulator to index Y.

Transfers the value in the accumulator to the index register Y. If the registers are different sizes, the nature of the transfer is determined by the Y register. TAY does not change the value in the accumulator.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nmost significant bit of the value transferred.
v
x0 = value transferred is 16 bits.
1 = the lower 8 bits of the accumulator are transferred.
z0 = result in y <> 0.
1 = result in y == 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTAY65c02$A821
Valid addressing modes.

TCD*

Transfer C accumulator to Direct Register.

Transfers the value in the 16-bit accumulator (C) to the Direct Page register D, regardless of the setting of the accumulator/memory mode flag.

An Alternate mnemonic is TAD (Transfer A accumulator to Direct Register).

If the A accumulator is set to just eight bits (whether because of the m flag or because the processor is in 6502 emulation mode), then its value becomes the low byte of the Direct Page register and the value in the hidden B accumulator becomes the high byte of the Direct Page register.

The accumulator’s 16 bit value is unchanged by the operation.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nSet to the most significant bit of the transferred value.
v
x
z0 = transferred value <> 0.
1 = transferred value == 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTCD (or TAD)65c816$5B21
Valid addressing modes.

TCS*

Transfer C accumulator to Stack Pointer register.

Transfers the value of the accumulator to the Stack Pointer S. The accumulator’s value is unchanged.

An alternate mnemonic is TAS (Transfer A accumulator to Stack Pointer register).

If the A accumulator is set to just eight bits (whether because of the m flag or because the processor is in 6502 emulation mode), then its value becomes the low byte of the Stack Pointer register and the value in the hidden B accumulator becomes the high byte of the Stack Pointer register.

The accumulator’s 16 bit value is unchanged by the operation.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nSet to the most significant bit of the transferred value.
v
x
z0 = transferred value <> 0.
1 = transferred value == 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTCS (or TAS)65c816$1B21
Valid addressing modes.

TDA*

Transfer Direct Page register to Accumulator.

Transfers the value in the 16-bit Direct Page register D to the 16-bit Accumulator C, regardless of the setting of the accumulator/memory mode flag.

An alternate mnemonic is TDC (Transfer Direct Page register to C Accumulator).

If the A accumulator is set to just 8 bits (whether because the m flag is set, or because the processor is in 6502 emulation mode), then it takes the value of the low byte of the Direct Page register and the hidden B accumulator takes the value of the high byte of the Direct Page register.

The Direct Page register’s 16-bit value is unchanged.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nthe most significant bit of the transferred value.
v
x
z0 = transferred value <> 0.
1 = transferred value == 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTDA (or TDC)65c816$7B21
Valid addressing modes.

TDC*

Transfer Direct Page register to C Accumulator.

Transfers the value in the 16-bit Direct Page register D to the 16-bit Accumulator C, regardless of the setting of the accumulator/memory mode flag.

An alternate mnemonic is TDA (Transfer Direct Page register to A Accumulator).

If the A accumulator is set to just 8 bits (whether because the m flag is set, or because the processor is in 6502 emulation mode), then it takes the value of the low byte of the Direct Page register and the hidden B accumulator takes the value of the high byte of the Direct Page register.

The Direct Page register’s 16-bit value is unchanged.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nthe most significant bit of the transferred value.
v
x
z0 = transferred value <> 0.
1 = transferred value == 0.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTDC (or TDA)65c816$7B21
Valid addressing modes.

TRB

Test and reset bit.

Logically “AND” together the complement of the value in the accumulator with the data at the effective address specified by the operand. Stores the result at the memory location.

This has the effect of clearing each memory bit for which the corresponding accumulator bit is set, while leaving unchanged all memory bits in which the corresponding accumulator bits are zeroes.

Unlike the BIT instruction, TRB is a read-modify-write instruction, not only calculating a result and modifying a flag, but also storing the result to memory.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
n
v
x
z0 = memory value AND’ed with accumulator value is nonzero.
1 = memory value AND’ed with accumulator value is zero
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteTRB addr65c02$1C6
+1 if m = 0.
3
direct page (dp)TRB dp65c02$145
+1 if m = 0.
+1 if low byte of dp register <> 0.
2
Valid addressing modes.

TSA*

Transfer Stack Pointer register to Accumulator.

Transfer the value in the 16-bit Stack Pointer S to the 16-bit accumulator A, regardless of the setting of the accumulator/memory mode flag.

An alternate mnemonic is TSC (Transfer the value in the Stack Pointer register to C accumulator).

If the A accumulator is set to just 8 bits (whether because the m flag is set or because the processor is in 6502 emulation mode), then it takes the value of the low byte of the stack pointer and the hidden B accumulator takes the value of the high byte of the stack pointer. In emulation mode, B will always take a value of one, since the stack is confined to page one.

The stack pointer’s value is unchanged.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nset to the most significant bit of the transferred value.
v
x
z0 = the transferred value is nonzero.
1 = the transferred value is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTSA (or TSC)65c816$3B21
Valid addressing modes.

TSB

Test and set bit.

Logically “OR” together the value in the accumulator with the data at the effective address specified by the operand. Store the result at the memory location.

This has the effect of setting each memory bit for which the corresponding accumulator bit is set, while leaving unchanged all memory bits in which the corresponding accumulator bits are zeroes.

Unlike the BIT instruction, TSB is a read-modify-write instruction, not only calculating a result and modifying a flag, but storing the result to memory.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
n
v
x
z0 = memory AND’ed with accumulator value is nonzero
1 = memory AND’ed with accumulator value is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
absoluteTSB addr65c02$0C6
+1 if m = 0.
3
direct pageTSB dp65c02$045
+1 if m = 0.
+1 if low byte of direct page register <> 0.
2
Valid addressing modes.

TSC*

Transfer Stack Pointer register to C accumulator.

Transfer the value in the 16-bit Stack Pointer S to the 16-bit accumulator C, regardless of the setting of the accumulator/memory mode flag.

An alternate mnemonic is TSA (Transfer the value in the Stack Pointer register to Accumulator).

If the A accumulator is set to just 8 bits (whether because the m flag is set or because the processor is in 6502 emulation mode), then it takes the value of the low byte of the stack pointer and the hidden B accumulator takes the value of the high byte of the stack pointer. In emulation mode, B will always take a value of one, since the stack is confined to page one.

The stack pointer’s value is unchanged.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nset to the most significant bit of the transferred value.
v
x
z0 = the transferred value is nonzero.
1 = the transferred value is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTSC (or TSA)65c816$3B21
Valid addressing modes.

TSX

Transfer Stack Pointer register to index X.

Transfers the value in the Stack Pointer S to the index register X. The Stack Pointer’s value is not changed.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nn is set to the most significant bit of the transferred value
v
x0 = the full 16 bit value in the stack pointer is transferred to the x register.
1 and 65c02 = only the low byte of the value in the stack pointer is transferred to the x register.
z0 = the transferred value is nonzero
1 = the transferred value is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTSX65c02$BA21
Valid addressing modes.

TXA

Transfer index X to Accumulator.

Transfer the value in index register X to the accumulator. If the registers are different sizes, the nature of the transfer is determined by the destination (accumulator). The value in the index register is not changed by the operation.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m0 = if the index register is 8 bits, those 8 bits are transferred to the low byte of the accumulator and the upper 8 bits are zeroed. if the index register is 16 bits, it is copied to the accumulator.
1 = if the index register is 8 bits, it is copied to the accumulator. if the index register is 16 bits, the lower 8 bits are stored in the accumulator and the upper 8 bits are ignored, the hidden B accumulator is not changed.
nset to the value of the most significant bit of the transferred value
v
x
z0 = transferred value is nonzero.
1 = transferred value is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTXA65c02$8A21
Valid addressing modes.

TXS

Transfer index X to Stack Pointer register.

Transfer the value in index register X to the Stack Pointer S. The index register’s value is not changed by the operation.

TXS, along with TCS are the only two instructions for changing the value in the Stack Pointer. The two are also the only two transfer instructions that do not alter the flags.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
n
v
x0 = the full 16 bit value in x is transferred to the stack pointer.
1 = the 8bit x register is transferred to the lower byte of the stack pointer. the upper byte of the stack pointer is zeroed.
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTXS65c02$9A21
Valid addressing modes.

TXY

Transfer index X to index Y.

Transfers the value in index register X to index register Y. The value in index register X is not changed.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nset to the most significant bit of the transferred value.
v
x0 = value transferred is 16 bits.
1 and 6502 = value transferred is 8 bits.
z0 = transferred value is nonzero.
1 = transferred value is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTXY65c816$9B21
Valid addressing modes.

TYA

Transfer index Y to accumulator.

Transfers the value in index register Y to the accumulator. If the registers are different sizes, the nature of the transfer is determined by the destination (accumulator). The value in the index register is not changed.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m0 = if x = 0, then the 16 bit contents of y are copied to the 16 bit accumulator. if x = 1 then the 8 bit index register is copied to the low byte of the accumulator and the high byte of the accumulator is zeroed.
1 = if x = 0, then the lower 8 bits of the 16 bit y are copied to the 8 bit accumulator. if x = 1 then the 8 bit y is copied to the 9 bit accumulator.
nset to the most significant bit of the transferred value.
v
x
z0 = transferred value is nonzero.
1 = transferred value is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTYA65c02$9821
Valid addressing modes.

TYX*

Transfer index Y to index X.

Transfers the value in index register Y to index register X. The value in index register Y is unchanged. Note that X and Y are never different sizes.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nset to the most significant bit of the transferred value.
v
x
z0 = transferred value is nonzero.
1 = transferred value is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedTYX65c816$BB21
Valid addressing modes.

WAI

Wait for interrupt.

Pulls the RDY pin low. Power consumption is reduced and RDY remains low until an external hardware interrupt is received (NMI, IRQ, ABORT or RESET).

WAI is designed to put the processor to sleep during an external event to reduce its power consumption, to allow it to be synchronized with an external event, and/or to reduce interrupt latency (an interrupt occurring during execution of an instruction is not acted upon until execution of the instruction is complete, perhaps many cycles later; WAIT ensures that an interrupt is recognized immediately).

Once an interrupt is received, control is vectored through one of the hardware interrupt vectors; an RTI from the interrupt handling routine will return control to the instruction following the original WAI. However, if by setting the i flag, interrupts have been disabled prior to the execution of the WAI instruction, and IRQ’ is asserted, the “wait” condition is terminated and control resumes with the next instruction, rather than through the interrupt vectors. This provides the quickest response to an interrupt, allowing synchronization with external events. WAI also frees up the bus; since RDY is pulled low in the third instruction cycle, the processor may be disconnected from the bus if BE is also pulled low.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedWAI65c816$CB3
+additional cycles required by interrupt to restart the processor.
1
Valid addressing modes.

WDM*

Reserved for future use.

This instruction was provided for future expansion of the instruction set to 16 bit opcodes. This opcode would signal that another instruction byte follows which would be an opcode in the expanded instruction set. It was given the temporary mnemonic WDM which are the initials of the processors’ designer, William D. Mensch, Jr.

WDM shouldn’t be used in a program, as it would introduce incompatibilities with possible future 65x processors. If it accidentally executed, it will act like a two-byte NOP instruction.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
n
v
x
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
WDM65c816$42?2?
Valid addressing modes.

XBA*

Exchange B and A accumulator.

B represents the high-order byte of the 16 bit C accumulator, and A in this case represents the low-order byte. XBA swaps the contents of the low-order and high-order bytes of C.

An alternate mnemonic is SWA (Swap the high and low bytes of the 16-bit A Accumulator).

XBA can be used to invert the low-order, high-order arrangement of a 16-bit value, or to temporarily store an 8-bit value from the A accumulator into B. Since it is an exchange, the previous contents of both accumulators are changed, replaced by the previous contents of the other.

Neither mode select flags nor the emulation mode flag affects this operation.

The flags are changed based on the new value of the low byte the A accumulator (that is, on the former value of the high byte, the B accumulator), even in 16 bit accumulator mode.

FlagEffect on ExecutionValue after Execution
c
d
e
i
m
nset to the most significant bit of the value that is transferred from the B accumulator to the A accumulator.
v
x
z0 = 8 bit value transferred to A accumulator is non-zero.
1 = 8 bit value transferred to A accumulator is zero.
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedXBA (or SWA)65c816$EB31
Valid addressing modes.

XCE*

Exchange carry and emulation bits.

This instruction is the only means provided by the 65c816 to shift between 65c02 emulation mode and the full, 16-bit native mode.

The emulation mode is used to provide hardware and software compatibility between the 65c02 and 65c816.

If the processor is in emulation mode, then to switch to native mode, first clear the carry bit, then execute an XCE. Since it is an exchange operation, the carry flag will reflect the previous state of the emulation bit. Switching to native mode causes bit five to stop functioning as the break flag, and function instead as the x mode select flag. A second mode select flag, m, uses bit six, which was unused in emulation mode. Both mode select flags are initially set to one (eight-bit modes). There are also other differences described in the text.

If the processor is in native mode, then to switch to emulation mode, you first set the carry bit, then execute an XCE. Switching to emulation mode causes the mode select flags (m and x) to be lost from the status register, with x replaced by the b break flag. This forces the accumulator to eight bits, but the high accumulator byte is preserved in the hidden B accumulator. It also forces the index registers to eight bits, causing the loss of values in their high bytes, and the stack to page one, causing the loss of the high byte of the previous stack address. There are also other differences described in the text

FlagEffect on ExecutionValue after Execution
ctakes emulation (e flag) bit’s previous value.
d
etakes carry (c flag) bit’s previous value.
i
m1
n
v
x1
z
Flags affecting operation.
AddressingSyntaxProcessorOpCodeCycles Bytes
impliedXCE65c816$FB21
Valid addressing modes.